06-23-2017 08:23 AM
I'm back, with a little issue with MIG...
I want to use DDR3 (Micron MT41K64M16TW-107) with artix-7.
I have generated the MIG. I have download the VHDL code for DDR3 simuation (with some mistakes). I get the Trafic generator example.
Everybody is connected, but nothing appened in simulation...
I generate the sys_clk at 333 MHz, reset at the begining.
Init_calib_complete never rise up (X).
My top level file is attached.
Some help will be greatfull!