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pgrangeray
Explorer
Explorer
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Registered: ‎05-31-2017

MIG ddr3_ck_* pin assignment problem

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Hello guys,

 

I'm back, with a little issue with MIG...

 

I want to use DDR3 (Micron MT41K64M16TW-107) with artix-7.

I have generated the MIG. I have download the VHDL code for DDR3 simuation (with some mistakes). I get the Trafic generator example.

Everybody is connected, but nothing appened in simulation...

 

I generate the sys_clk at 333 MHz, reset at the begining.

Init_calib_complete never rise up (X).

 

My top level file is attached.

 

Some help will be greatfull!

 

Thank you!

 

Capture.JPG

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pgrangeray
Explorer
Explorer
4,323 Views
Registered: ‎05-31-2017
Problem solved!

clk_ref always at 0...

I had to read more about sys_clk and ref_clk !

View solution in original post

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pgrangeray
Explorer
Explorer
4,324 Views
Registered: ‎05-31-2017
Problem solved!

clk_ref always at 0...

I had to read more about sys_clk and ref_clk !

View solution in original post

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