My problem is about Clock glitch or sideband. ML605 Evalboard clock output has glitch like "Picture 1"
How can i eliminate this glitch?
Summary of my setup, AD9523 Clock Generator output is connected to ML605 Differential Input pin.
ML605 output is connected to spectrum analyzer. All my signal define LVDS
there is always the possibiity to add jitter or phase noise to the clock.
It could be that there is a lot of switching going on in the FPGA and the noise on VCCINT is getting coupled onto the clock.
What design is running on the FPGA?
Can you run a cut down design with not a lot switching going on?
You could look at using a PLL or MMCM to try filter some of the jitter...
If this is a big design then you could look at switching some of the design on a different clock edge that would reduce the noise on VCCINT...
What does this clock look like in the time domain in each case?