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Visitor
Visitor
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Registered: ‎06-10-2019

MMCM DRP using fractional numbers

I am trying to improve that code adding more function, like controlling MMCM attributes.
 
 
Mainly i am concerning with;  CLKFBOUT_MULT_F which is "M",  DIVCLK_DIVIDE  which is "D",  CLKOUT[0]_DIVIDE_F which is "O" given in UG472 user guide in page 83.
 
In the code that i linked it above basicly we are controlling "O" dividers. I added "M" and "D" features using registers given in XAPP888.pdf file and works fine for integer numbers. However i could not add fractional controls to output 0 or "M" counter.
 
According to XAPP888 page 6 table 1&2, 
 
if i apply:
DADDR <= "0001000"  -- 0x08
DI <= "000 1 000100 000100"  -- divide by 8, 4 High, 4 Low 
 
then apply:
DADDR <= "0001001"  -- 0x09
DI <= "1 010 1 1 00 0 0 00000"  --FRAC [14:12] = 010 which is 2 x 0.125 = 0.25
 
With these reconfigurations, i should get 8.25 value for "O" counter. 
 
I am guessing same logic could be set up for "M" counter applying register table 7 given in xapp file.
 
When i did these things i lose locked signal and my clock output is gone. Could anyone explain me what i am doing wrong? 
 
 
 
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Moderator
Moderator
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Registered: ‎04-18-2011

Hi @inspiron 

Can you tell us what happens when you use the state machine provided with the XAPP. This should manage the writes to the MMCM. 

In this case you pass it the desired settings and the functions in the header file manage the write. 

Try it out this way and see if it works. 

After that you can look at setting the DRP access up in the wizard. 

 

Keith 

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Highlighted
Visitor
Visitor
502 Views
Registered: ‎06-10-2019

hi

thank you for your reply

 

i am not using xapp reference design.

i wrote a vhdl code calling MMCM2E_ADV as an instantiation. 

There is an FSM and my code is like shown in below

when state1 =>
state <= state2;
daddr <= 0x07; -- CLKOUT0 Register 1
din <= "0001" & "000100" & "000100"; -- 4 High 4 Low divide by 8
den <='1';
dwe <='1';

when state2 =>
state <= reset_state1;
daddr <= 0x08; -- CLKOUT0 Register 2
din <= "1010" & "100000" & "000000"; -- frac_en=1, frac[14:12]=010=0.125x2=0.25
den <='1';
dwe <='1';

when reset_state1 =>
state <= reset_state0;
mmcm_rst <= '1';

when reset_state0 =>
state <= reset_state0;
mmcm_rst <= '0';

This fsm located in a process, and triggers in every rising edge. 

State1 means that, clk out 0 should be divided by 8. 

State2 means that, wait there is a fractional here, you should divide it 8.25. 

 

Am i right?

By the way, i can change M, D and O counters without using fractional circuitry with these logic. I am just struggling with fractional case.

 

Actually it is similar to that code written by Hamster:  https://forum.digilentinc.com/topic/4180-mmcm-dynamic-clocking/

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Visitor
Visitor
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Registered: ‎06-10-2019

sorry for typo, daddr should be "0001000" in state1 (0x08), "0001001" in state2 (0x09)

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