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Explorer
Explorer
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Registered: ‎08-04-2016

MMCM Dynamic Reconfiguration

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Hello,

 

 

I am following xapp888 to dynamically reconfigure the MMCM.

If I set CLKFBOUT_MULT = 58.625 in the clock wizard, and then read the MMCM registers, I get that that CLKFBOUT Reg1 has a value of 0x171C. But 0x171C corresponds to a divide value of 28 high + 28 low = 56, not 58.

If I set CLKFBOUT_MULT = 58, then the same register has 0x175D which is correct (29 high + 29 low).

 

Doesn't the integer part of CLKFBOUT_MULT depend purely on the value in the CLKFBOUT Reg1?

If yes, why is there the above discrepancy?

If no, which other register affects it?

 

PS: The lock and filter registers are being set by the clocking wizard. I am only reading the registers at the moment.

 

(I had posted this question in the Timing Analysis forum, but that might be the wrong forum for this question)

 

Thanks,

Rajat Rao

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2007

Fractional divide uses two non-fractional counters and additional state and adder logic. It’s a bit hard to explain but I will give it shot. The 2 counters take different phases from the VCO. Assume a div of 2.5. Then counter A would take phase 0 and counter B would take phase 4 (180 degree offset). Output starts high with counter A, goes low with second rising edge counter B, goes high again with second rising edge of counter A after that, and so on. That results in a div value of 2.5. High/low time for the counters is 0 in this case because 2 edges are already combined for the fractional. For a div of 4.5 the high/low count would be 1 each. For 6.5 high/low would be 2 each. That is why you see 56 instead of 58.

 

 

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Xilinx Employee
Xilinx Employee
7,972 Views
Registered: ‎10-11-2007

Fractional divide uses two non-fractional counters and additional state and adder logic. It’s a bit hard to explain but I will give it shot. The 2 counters take different phases from the VCO. Assume a div of 2.5. Then counter A would take phase 0 and counter B would take phase 4 (180 degree offset). Output starts high with counter A, goes low with second rising edge counter B, goes high again with second rising edge of counter A after that, and so on. That results in a div value of 2.5. High/low time for the counters is 0 in this case because 2 edges are already combined for the fractional. For a div of 4.5 the high/low count would be 1 each. For 6.5 high/low would be 2 each. That is why you see 56 instead of 58.

 

 

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Explorer
Explorer
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Registered: ‎08-04-2016

Hello,

 

Thanks for the reply and good explanation.

 

What about CLKOUT0 high and low counter? Does the same principle apply?

 

I am trying to simulate my design (Post-Synthesis Simulation) but it seems the MMCM simulation model isn't complete.

When I change the value in CLKFBOUT Reg1, and not change the Lock and Filter Registers, the clock 'locked' signal goes high after a while and the clk_out present is the desired value. But this doesn't work on hardware (obviously because Lock and Filter registers are required). How do I solve this problem?

 

Thanks,

Rajat Rao

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Explorer
Explorer
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Registered: ‎08-04-2016

Which document lists the algorithm to calculate the register values based on the desired frequency?

 

Thanks,

Rajat Rao

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2007

Sorry for the delay. Out of office.

 

HT/LT still applies. It's just that in the fractional case the first "high/low" time is created by combining the two counters. So, as I said before, for a div2.5 instead of 1/1 you would get 0/0. 

 

Which version of the tools are you using? There were some mismatches between the xapp and the sim models. Both at fault. So please download the latest version of the xapp. There may still be some mismatches because I don't recall which version of the tools have all the fixes.

 

But it's not something to be be really worried about. Hardware should work unless the values are way out of line. The lock and filter settings represent the optimal settings, but usually will work just fine even if not set to the optimal loop filter/lock values.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2007

In xapp888 look at the explanation for the "MMCM and PLL Configuration Bit Groups". I think that is what you are looking for?

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