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Observer squaringcircle
Observer
544 Views
Registered: ‎12-19-2018

MMCM/PLL to align a reference frequency to an external freq

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Hello fellow FPGA developers,

 

I have a design in mind and wanted to get your inputs on whether this is possible/feasible or not.


Starting point:

 - I have an accurate & stable reference frequency 1 internal (e.g. 100MHz)

- I have an external frequency 2 (e.g. 20MHz) which sometimes stops for up to several milliseconds

 

I need a phase & frequency synchronous signal aligned to frequency 2 - the external one with interrupts.

Ideally, the new signal is always available, even if the external clock is stopped (for no more than 10ms for example).

 

My idea is to have an internal PLL1 which will synchronize the reference clock of 100MHz as close as possible to the external reference (e.g. 5x ext. freq.) and hold the actual setting while the external clock is stopped.

I have a PLL 2 which uses the external clock as input 1, and my internal reference as input 2. Whenever the external frequency stops, I'd switch back to the internal reference.

A phase drift during the time when the external clock is stopped is ok.

 

My questions are:

- Is this idea feasible?

- in case it is, are there any known issues/restrictions associated with it?

- Will the lock time of PLL2 be reduced if both inputs are better aligned at the start? (e.g. smaller frequency offset between input 1 & 2?)

- do the internal PLLs / MMCMs support a holdover capability like external PLLs do in some cases?

 

Many thanks, upfront for any feedback.

If my concept is not good and anyone has a better idea, I'd be grateful to hear more about it.

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1 Solution

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Historian
Historian
404 Views
Registered: ‎01-23-2009

Re: MMCM/PLL to align a reference frequency to an external freq

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An OSERDES can help if you are trying to send this clock out of the FPGA.

Internal clocks in the FPGA can be in ranges up to a bit more than 500MHz, but things get difficult at the faster speeds - operating around 200MHz is a nice sweet spot for most stuff. The IO though can run much faster than this. So, you can run the inside of your FPGA at 200MHz but have the output run at 800MHz DDR - effectively putting out 8 phases of this output "clock" (really just a digital signal) on each high 800MHz 1/2 clock. With this, your jitter is only 1/1600MHz (625ps) , whereas if you are operating only on the 200MHz clock, it is 1/200MHz (5ns).

But this only works for external clocks - you cannot use the output of an OSERDES internally in the FPGA.

As for using an internal PLL/MMCM to filter this, you can't (or shouldn't) access the CLKIN of an MMCM from the fabric. Furthermore the maximum input clock jitter is 20% of the input clock period or 1ns - so maybe the output of the OSERDES (which you would have to feed back on the board to a clock capable input) might work. But even at that, the PLL/MMCMs in the FPGA are not really made for filtering large amounts of jitter - the output jitter might still be pretty nasty. You would need to use an external jitter filtering PLL to get a reasonable clock out of this.

You mention that you are trying to use this as the clock to an "external data converter" - you mean an ADC? If so, this is a problem - analog devices need really clean clocks for good conversion; clock jitter causes sampling error...

Avrum

11 Replies
Moderator
Moderator
501 Views
Registered: ‎04-18-2011

Re: MMCM/PLL to align a reference frequency to an external freq

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 - I have an accurate & stable reference frequency 1 internal (e.g. 100MHz)

what do you mean by internal here? how do you make this internal clock? I've never heard of a way to do it inside the FPGA without taking some external clock and synthesizing the new frequency with an MMCM or PLL. 

 

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Observer squaringcircle
Observer
499 Views
Registered: ‎12-19-2018

Re: MMCM/PLL to align a reference frequency to an external freq

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@klumsde ,

 

Thanks for your feedback. I have been a bitunprecise in my wording. This clock is available internally, but comes from an external PLL sourced by a temperature compensated oscillator.

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Explorer
Explorer
489 Views
Registered: ‎09-13-2011

Re: MMCM/PLL to align a reference frequency to an external freq

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If I understand correctly you want an output clock that is stable even when the input clock sometimes cuts off - and you have another clock source for this.

I probably wouldn't do clock switching, that's like asking for trouble, would make more sense to me to use an external VCXO or NCO that you can adjust to the wanted output phase and frequency. Then you need some simple mechanism like a P-regulator (or PI) to make the output clock to be in perfect sync with the cutting clock when it's there. When the input clock cuts the regulator should stay in place so the same frequency and phase will be held, and when it comes back again it will regulate again if there was a small skew.

The output of the VCXO/NCO can also be brought back into the FPGA, can even the clock that produces your 100MHz.

Observer squaringcircle
Observer
477 Views
Registered: ‎12-19-2018

Re: MMCM/PLL to align a reference frequency to an external freq

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@tsjorgensen 

 

Many thanks for the detailed explanation. Your understanding of the situation is correct.

I think I understand your idea, and consider it good.

However, my problem is that I need to do this on existing hardware, which has no external clock sources other than the ones already mentioned.

 

Is there a chance to accomplish this task by combining internal PLLs?

 

 

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Scholar dgisselq
Scholar
470 Views
Registered: ‎05-21-2015

Re: MMCM/PLL to align a reference frequency to an external freq

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@squaringcircle,

I would try to accomplish this problem with a simple bit of logic, similar to this one.

At issue would be, how much phase noise can you handle?

Dan

Historian
Historian
460 Views
Registered: ‎01-23-2009

Re: MMCM/PLL to align a reference frequency to an external freq

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As far as I know, the internal PLLs/MMCMs have no such capability (although the Spartan-6 DCMs have some capability in this regard). For the PLLs/MMCMs, if the input clock stops, the PLLs will lose lock.

How much jitter can you tolerate on this clock, and does it have to be a real "clock"? 

If you only need a correct "average frequency" then you might build this completely in digital logic using the "stable" clock. You can effectively count the average number of higher frequency clock periods in your unstable input clock when the input clock is running, and then mimic (hold) that when your input clock stops. Using a concept similar to a Direct Digital Synthesizer (DDS) you can carry as many "fractional" bits as you want to reconstruct the long term frequency of the input clock.

However, done this way, the reconstructed "clock" is really an enable on the stable (fast) clock, and will have a large jitter; one complete period of the fast clock. If you can tolerate both of these, then this can be a solution.

Avrum

Tags (1)
Scholar dgisselq
Scholar
446 Views
Registered: ‎05-21-2015

Re: MMCM/PLL to align a reference frequency to an external freq

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An OSERDES can be used to keep the jitter to a minimum.  Whether that minimum is "minimum enough" is another question.

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Observer squaringcircle
Observer
413 Views
Registered: ‎12-19-2018

Re: MMCM/PLL to align a reference frequency to an external freq

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Many thanks for all your replies.

To answer some of the questions:

Phase noise is an issue to an extent, as the clock will be used for an external data converter. However, using this clock, it might be possible to drive another PLL internal of the FPGA?

I don't really understand how the OSERDES can help cleaning clock jitter - purely because I don't know this part of the FPGA at all.

Could you please provide more details on this idea?

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Historian
Historian
405 Views
Registered: ‎01-23-2009

Re: MMCM/PLL to align a reference frequency to an external freq

Jump to solution

An OSERDES can help if you are trying to send this clock out of the FPGA.

Internal clocks in the FPGA can be in ranges up to a bit more than 500MHz, but things get difficult at the faster speeds - operating around 200MHz is a nice sweet spot for most stuff. The IO though can run much faster than this. So, you can run the inside of your FPGA at 200MHz but have the output run at 800MHz DDR - effectively putting out 8 phases of this output "clock" (really just a digital signal) on each high 800MHz 1/2 clock. With this, your jitter is only 1/1600MHz (625ps) , whereas if you are operating only on the 200MHz clock, it is 1/200MHz (5ns).

But this only works for external clocks - you cannot use the output of an OSERDES internally in the FPGA.

As for using an internal PLL/MMCM to filter this, you can't (or shouldn't) access the CLKIN of an MMCM from the fabric. Furthermore the maximum input clock jitter is 20% of the input clock period or 1ns - so maybe the output of the OSERDES (which you would have to feed back on the board to a clock capable input) might work. But even at that, the PLL/MMCMs in the FPGA are not really made for filtering large amounts of jitter - the output jitter might still be pretty nasty. You would need to use an external jitter filtering PLL to get a reasonable clock out of this.

You mention that you are trying to use this as the clock to an "external data converter" - you mean an ADC? If so, this is a problem - analog devices need really clean clocks for good conversion; clock jitter causes sampling error...

Avrum

Highlighted
Scholar dgisselq
Scholar
389 Views
Registered: ‎05-21-2015

Re: MMCM/PLL to align a reference frequency to an external freq

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Observer squaringcircle
Observer
370 Views
Registered: ‎12-19-2018

Re: MMCM/PLL to align a reference frequency to an external freq

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Hello all,

 

First of all, many thanks for your good and detailed inputs.

@dgisselq that article was reall helpful as well.

Fortunately, I found a path on hardware that allows to have a clock output to a physical pin and then back into the FPGA on a global clock net capable pin pair.

I'll try to setup as described by you guys and the article.

 

Again - thanks for all your support.

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