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Observer
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Registered: ‎05-01-2018

## MMCM clock edge alignment

For an MCMM that is configured with feedback, we are generating a clk_1x and a clk_2x output.   Based on the clk_in, is there a guaranteed alignment between the rising edge of clk_2x and the rising edge of clk_in?

Is this a guaranteed relationship?

clk_in      ________|^^^^^^^^|________|^^^^^^^^|

clk_2x             ____|^^^^|___|^^^^|____|^^^^|___|

Or can the MMCM create this?  (falling edge aligned with rising edge)

clk_in      ________|^^^^^^^^|________|^^^^^^^^|

clk_2x                     |___|^^^^|____|^^^^|___|^^^^|___

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Guide
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Registered: ‎01-23-2009

## Re: MMCM clock edge alignment

First it is important to recognize exactly what is synchronized to what in an MMCM.

Before we look at the input/output relationship, lets look at the relationship between the different output of the MMCM. Assuming you set the desired phase relationship between the outputs to 0, then

• The rising edges of all clocks will be in phase at least once ever common multiple of period
• So a 1x and a 2x output will be in phase during all rising edges of the 1x clock
• a 2x and a 3x clock will be in phase every 2nd rising edge of the 2x clock with every 3rd rising edge of the 3x clock (etc...)
• The in phase edges will be "very close" to each other - the error on this phase is specified by MMCM_Tstatphaoffset
• See the datasheet for the family and speedgrade you are using - as an example for Kintex-7 this is 120ps

Now let's look at the relationship between the input and output clocks. The MMCM works to keep the CLKIN and CLKFBIN input to the MMCM in phase. Since the CLKFBIN is connected to the CLKFBOUT through one of a couple of different types of connections, the CLKIN to CLKFBOUT relationship is determined by the cells on the path from CLKFBOUT to CLKFBIN. Specifically, if, for example, a BUFG is used between CLKFBOUT and CLKFBIN (which is the normal connection for "clock deskew" the the CLKOUT will lead the CLKFBIN (and hence the CLKIN) by the delay through the BUFG (and the global clock network). Furthermore there is some special additional compensation when the CLKIN comes directly from an IBUF; the MMCM cancels this out too. The goal of this is to ensure that the clock at the leaves of the global clock network (which would be the ones clocking capture flip-flops on an input interface) are in phase with the clock at the pin of the FPGA (so that you can capture interfaces using clocks on clock capable pins).

And, of course, the CLKFBOUT is simply another output of the MMCM, so the phase error between the CLKFBOUT and the other CLKOUTx outputs are governed by MMCM_Tstatphaoffset. So the relationship between CLKIN and CLKOUT is the same as CLKIN to CLKFBOUT (+/- MMCM_Tstatphaoffset).

But, as I said, the CLKIN and CLKFBIN will always be in phase (rising edge to rising edge - they are both 1x clocks) - so the phase of CLKOUT will be earlier by the propagation of the connection from CLKFBOUT to CLKFBIN.

Avrum

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Moderator
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Registered: ‎02-09-2017

## Re: MMCM clock edge alignment

Hi @rillemam,

The output clocks of the MMCM/PLL are always aligned at  0°. For it to be aligned at the falling edge, you would have to explicitly configure the clk_2x to be phase shifted by 90°.

Otherwise, they will all be aligned at 0°, because those clocks are generated from the same MMCM internal reference clock.

There's some more information about it in the document UltraScale Architecture Clocking Resources - UG572, pg. 57.

Thanks,

Andre Guerrero

Product Applications Engineer

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Highlighted
Guide
991 Views
Registered: ‎01-23-2009

## Re: MMCM clock edge alignment

First it is important to recognize exactly what is synchronized to what in an MMCM.

Before we look at the input/output relationship, lets look at the relationship between the different output of the MMCM. Assuming you set the desired phase relationship between the outputs to 0, then

• The rising edges of all clocks will be in phase at least once ever common multiple of period
• So a 1x and a 2x output will be in phase during all rising edges of the 1x clock
• a 2x and a 3x clock will be in phase every 2nd rising edge of the 2x clock with every 3rd rising edge of the 3x clock (etc...)
• The in phase edges will be "very close" to each other - the error on this phase is specified by MMCM_Tstatphaoffset
• See the datasheet for the family and speedgrade you are using - as an example for Kintex-7 this is 120ps

Now let's look at the relationship between the input and output clocks. The MMCM works to keep the CLKIN and CLKFBIN input to the MMCM in phase. Since the CLKFBIN is connected to the CLKFBOUT through one of a couple of different types of connections, the CLKIN to CLKFBOUT relationship is determined by the cells on the path from CLKFBOUT to CLKFBIN. Specifically, if, for example, a BUFG is used between CLKFBOUT and CLKFBIN (which is the normal connection for "clock deskew" the the CLKOUT will lead the CLKFBIN (and hence the CLKIN) by the delay through the BUFG (and the global clock network). Furthermore there is some special additional compensation when the CLKIN comes directly from an IBUF; the MMCM cancels this out too. The goal of this is to ensure that the clock at the leaves of the global clock network (which would be the ones clocking capture flip-flops on an input interface) are in phase with the clock at the pin of the FPGA (so that you can capture interfaces using clocks on clock capable pins).

And, of course, the CLKFBOUT is simply another output of the MMCM, so the phase error between the CLKFBOUT and the other CLKOUTx outputs are governed by MMCM_Tstatphaoffset. So the relationship between CLKIN and CLKOUT is the same as CLKIN to CLKFBOUT (+/- MMCM_Tstatphaoffset).

But, as I said, the CLKIN and CLKFBIN will always be in phase (rising edge to rising edge - they are both 1x clocks) - so the phase of CLKOUT will be earlier by the propagation of the connection from CLKFBOUT to CLKFBIN.

Avrum

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Observer
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Registered: ‎05-01-2018