07-18-2017 01:01 PM
I have been trying to simulate dynamic phase shifting in a 7-series MMCM module. I assert psen for one clock cycle, then wait for over twelve cycles of the psclk, but psdone always stays low. Also if I look down inside the MMCME2_ADV primitive, none of the ps signals look to be toggling or doing anything when I send psen. I made this module with the clock wizard, but the MMCME2_ADV seems to be configured correctly when I look at the source.
*I reset the MMCM at the beginning of my simulation.
*I am not trying to shift the phase until thousands of ns after the MMCM has locked.
*I remembered to enable the dynamic phase shift feature, and to enable fine phase shift on my output clocks, when I was configuring the clock wizard.
*The psclk is running, and psen is synchronous to it.
*I have tried both incrementing and decrementing; results are the same.
*The Vivado version used is 2017.1; the clock wizard IP version is 5.4
07-18-2017 08:52 PM
Are you observing this behavior in simulation?
If yes, share the simulation snapshot here.
What is the frequency of PSCLK? Is PSCLK clean?
07-19-2017 08:23 AM
Here is a screenshot. The top-level signals locked, psclk, psen, psincdec, and psdone are at the bottom. Everything else is from inside the MMCM.
Yes psclk is clean. It is running at 125 MHz.
07-15-2019 09:45 AM
It looks like this was never resolved. Sadly I am seeing the same thing while simulating in Modelsim with models generated by Vivado 2019.1.
09-19-2019 08:08 AM
I had the same problem, using the MMCME2_ADV in VCS: psdone never asserted. I was using my firm's precompiled libraries. (I instantiated the primitive myself; I didn't use the wizard.) Then I tried recompiling the source (Vivado/data/verilog/src/unisims/MMCME2_ADV.v, version 2017.1, last revised 11/26/2014) into my work library and then it started working. I don't understand why; I think the precompiled version I had been using was from the same source, but something must have been different.
03-12-2020 10:05 PM - edited 03-12-2020 10:16 PM
#1 make sure that you select USE fine PS in the clocking wizard IP
#2 When using the direct primitive instantiation, Make sure that you set the below attribute.