07-19-2018 06:50 AM
I am having issues with the MMCM fine phase shifting. I had the phase shifting working, and at a certain point after rerunning the synthesis & implementation it stopped working while nothing has changed related to the Clock wizard IP's. I am using vivado 2018.2 and clock wizard v6.0 But I have had the same issue on version 2018.1 with IP version 5.7(i think).
Resetting the output products of the BD does not help, nor does rerunning the design runs.
What could cause this?
07-23-2018 05:13 PM
Hi @tlapauw,
You found the right information there. The Fine Phase Shift is not allowed / supported at any time, while also using the DRP function.
If you really need to use the DRP resources, you may have to use the Static Phase Shift instead, which is supported. Please not that the SPS has a coarser granularity, so you might not be able to achieve exactly the same phases you would with the DPS.
Thanks,
07-19-2018 06:56 AM
when you say, "stopped working", are you referring to the behavior you observe in the silicon? I recommend that you open the routed design in Vivado, find the MMCM primitive, and then do a dump of all the properties on that MMCM. Post them here, and the issue ought to be fairly clear.
07-19-2018 07:13 AM
07-19-2018 02:43 PM
No, these are the parameters on the clock wizard wrapper, not the fundamental properties of the MMCM primitive cell in the design netlist. Dig into the netlist when you open the design. Hit control F to do a search for primitive cells with type MMCM, and you'll be able to find it pretty easily.
07-20-2018
12:27 AM
- last edited on
11-30-2018
07:20 AM
by
arunyan
This should be it right (I am still somewhat trying to find my way in vivado). But thank you already for your time so far.
ADV_USEFUL_SKEW false ASYNC_REG false BANDWIDTH OPTIMIZED BEL MMCME2_ADV.MMCME2_ADV BLKNM BLOCK_SYNTH.ADDER_THRESHOLD 16 BLOCK_SYNTH.AUTO_PIPELINING -1 BLOCK_SYNTH.COMPARATOR_THRESHOLD 16 BLOCK_SYNTH.CONTROL_SET_THRESHOLD 2 BLOCK_SYNTH.EXTRACT_PARTITION -1 BLOCK_SYNTH.FLATTEN_HIERARCHY BLOCK_SYNTH.FLATTEN_INSIDE_PARTITION -1 BLOCK_SYNTH.FSM_EXTRACTION BLOCK_SYNTH.KEEP_EQUIVALENT_REGISTER -1 BLOCK_SYNTH.LUT_COMBINING -1 BLOCK_SYNTH.MAX_LUT_INPUT 6 BLOCK_SYNTH.MUXF_MAPPING -1 BLOCK_SYNTH.PRESERVE_BOUNDARY -1 BLOCK_SYNTH.RETIMING -1 BLOCK_SYNTH.ROM_MAPPING -1 BLOCK_SYNTH.SHREG_MIN_SIZE 3 BLOCK_SYNTH.STRATEGY DEFAULT BLOCK_SYNTH.USER_PROVIDED BOX_TYPE PRIMITIVE BUFG CLK CAPACITANCE CARRY_REMAP 1 CASCADE_HEIGHT -1 CELL_BLOAT_FACTOR CLASS cell CLKFBOUT_MULT_F 50.0 CLKFBOUT_PHASE 180.0 CLKFBOUT_USE_FINE_PS true CLKIN1_PERIOD 50.0 CLKIN2_PERIOD 0.0 CLKOUT0_DIVIDE_F 50.0 CLKOUT0_DUTY_CYCLE 0.5 CLKOUT0_PHASE 0.0 CLKOUT0_USE_FINE_PS false CLKOUT1_DIVIDE 1 CLKOUT1_DUTY_CYCLE 0.5 CLKOUT1_PHASE 0.0 CLKOUT1_USE_FINE_PS false CLKOUT2_DIVIDE 1 CLKOUT2_DUTY_CYCLE 0.5 CLKOUT2_PHASE 0.0 CLKOUT2_USE_FINE_PS false CLKOUT3_DIVIDE 1 CLKOUT3_DUTY_CYCLE 0.5 CLKOUT3_PHASE 0.0 CLKOUT3_USE_FINE_PS false CLKOUT4_CASCADE false CLKOUT4_DIVIDE 1 CLKOUT4_DUTY_CYCLE 0.5 CLKOUT4_PHASE 0.0 CLKOUT4_USE_FINE_PS false CLKOUT5_DIVIDE 1 CLKOUT5_DUTY_CYCLE 0.5 CLKOUT5_PHASE 0.0 CLKOUT5_USE_FINE_PS false CLKOUT6_DIVIDE 1 CLKOUT6_DUTY_CYCLE 0.5 CLKOUT6_PHASE 0.0 CLKOUT6_USE_FINE_PS false CLOCK_REGION COMPENSATION BUF_IN CONTROL_SET_REMAP NONE CONVERT_BRAM8 false CORE_GENERATION_INFO C_AUX_RESET_HIGH C_AUX_RST_WIDTH 0 C_DM_WIDTH 0 C_DQS_WIDTH 0 C_DQ_WIDTH 0 C_EMIO_GPIO_WIDTH 0 C_EN_EMIO_ENET0 0 C_EN_EMIO_ENET1 0 C_EN_EMIO_PJTAG 0 C_EN_EMIO_TRACE 0 C_EXT_RESET_HIGH C_EXT_RST_WIDTH 0 C_FAMILY C_FCLK_CLK0_BUF C_FCLK_CLK1_BUF C_FCLK_CLK2_BUF C_FCLK_CLK3_BUF C_GP0_EN_MODIFIABLE_TXN 0 C_GP1_EN_MODIFIABLE_TXN 0 C_INCLUDE_ACP_TRANS_CHECK 0 C_INCLUDE_TRACE_BUFFER 0 C_IRQ_F2P_MODE C_MIO_PRIMITIVE 0 C_M_AXI_GP0_ENABLE_STATIC_REMAP 0 C_M_AXI_GP0_ID_WIDTH 0 C_M_AXI_GP0_THREAD_ID_WIDTH 0 C_M_AXI_GP1_ENABLE_STATIC_REMAP 0 C_M_AXI_GP1_ID_WIDTH 0 C_M_AXI_GP1_THREAD_ID_WIDTH 0 C_NUM_BUS_RST 0 C_NUM_F2P_INTR_INPUTS 0 C_NUM_INTERCONNECT_ARESETN 0 C_NUM_PERP_ARESETN 0 C_NUM_PERP_RST 0 C_PACKAGE_NAME C_PS7_SI_REV C_S_AXI_ACP_ARUSER_VAL 0 C_S_AXI_ACP_AWUSER_VAL 0 C_S_AXI_ACP_ID_WIDTH 0 C_S_AXI_ADDR_WIDTH 0 C_S_AXI_DATA_WIDTH 0 C_S_AXI_GP0_ID_WIDTH 0 C_S_AXI_GP1_ID_WIDTH 0 C_S_AXI_HP0_DATA_WIDTH 0 C_S_AXI_HP0_ID_WIDTH 0 C_S_AXI_HP1_DATA_WIDTH 0 C_S_AXI_HP1_ID_WIDTH 0 C_S_AXI_HP2_DATA_WIDTH 0 C_S_AXI_HP2_ID_WIDTH 0 C_S_AXI_HP3_DATA_WIDTH 0 C_S_AXI_HP3_ID_WIDTH 0 C_TRACE_BUFFER_CLOCK_DELAY 0 C_TRACE_BUFFER_FIFO_SIZE 0 C_TRACE_INTERNAL_WIDTH 0 C_TRACE_PIPELINE_WIDTH 0 C_USE_AXI_NONSECURE 0 C_USE_DEFAULT_ACP_USER_VAL 0 C_USE_M_AXI_GP0 0 C_USE_M_AXI_GP1 0 C_USE_S_AXI_ACP 0 C_USE_S_AXI_GP0 0 C_USE_S_AXI_GP1 0 C_USE_S_AXI_HP0 0 C_USE_S_AXI_HP1 0 C_USE_S_AXI_HP2 0 C_USE_S_AXI_HP3 0 DCI_VALUE 50 DELAY_BYPASS false DIVCLK_DIVIDE 1 DONT_PARTITION false DONT_TOUCH false DSP_FOLDING false DowngradeIPIdentifiedWarnings EXTRACT_ENABLE false EXTRACT_RESET false FILE_NAME d:/Pintail_WorkingDir/Ottawa/firmware/OttawaV1/OttawaV1.srcs/sources_1/bd/TOP/ip/TOP_clk_wiz_0_3/TOP_clk_wiz_0_3_clk_wiz.v FSM_ENCODED_STATES FSM_ENCODING auto FSM_SAFE_STATE none HBLKNM HD.ISOLATED false HD.ISOLATED_EXEMPT false HD.PLATFORM false HD.PLATFORM_WRAPPER false HD.RECONFIGURABLE false HD.RECONFIGURABLE_CONTAINER false HD.RECONFIGURABLE_CONTAINER_PLACEMENT_RANGE HD.RECONFIGURABLE_CONTAINER_ROUTING_RANGE HD.RECONFIG_PLATFORM false HD.SHELL false HD.TANDEM 0 HLUTNM HW_HANDOFF H_SET IBUF_DELAY_VALUE IFD_DELAY_VALUE INIT_VAL IOB AUTO IOBDELAY NONE IOB_TRI_REG false IODELAY_GROUP IPROGRAMMING IS_BEL_FIXED false IS_BLACKBOX false IS_CE_INVERTED IS_CLKINSEL_INVERTED 1'b0 IS_CLOCK_GATED false IS_DEBUGGABLE true IS_FANOUT_CONSTRAINED 0 IS_LOC_FIXED false IS_MATCHED true IS_ORIG_CELL false IS_PRIMITIVE true IS_PSEN_INVERTED 1'b0 IS_PSINCDEC_INVERTED 1'b0 IS_PWRDWN_INVERTED 1'b0 IS_REUSED false IS_RST_INVERTED 1'b0 IS_SEQUENTIAL true IS_S_INVERTED KEEP false KEEP_HIERARCHY TRUE KEEP_PRSHELL_DISCONNECT true LINE_NUMBER 149 LOC MMCME2_ADV_X0Y0 LOCK_PINS LOPT_BUFG_MISC false LUTNM LUT_REMAP false MACRO_NAME MAX_FANOUT MEM.ADDRESS_BEGIN 0 MEM.ADDRESS_END 0 MEM.ADDRESS_SPACE true MEM.ADDRESS_SPACE_BEGIN 0 MEM.ADDRESS_SPACE_DATA_LSB 0 MEM.ADDRESS_SPACE_DATA_MSB 0 MEM.ADDRESS_SPACE_DATA_WIDTH 0 MEM.ADDRESS_SPACE_END 0 MEM.ADDRESS_SPACE_WORD_WIDTH 0 MEM.CORE_MEMORY_WIDTH 0 MEM.DATA_LSB 0 MEM.DATA_MSB 0 MEM.ENDIANNESS LITTLE MEM.PORTA.ADDRESS_BEGIN 0 MEM.PORTA.ADDRESS_END 0 MEM.PORTA.DATA_BIT_LAYOUT MEM.PORTA.DATA_LSB 0 MEM.PORTA.DATA_MSB 0 MEM.PORTB.ADDRESS_BEGIN 0 MEM.PORTB.ADDRESS_END 0 MEM.PORTB.DATA_BIT_LAYOUT MEM.PORTB.DATA_LSB 0 MEM.PORTB.DATA_MSB 0 METHODOLOGY_DRC_VIOS MUXF_REMAP false NAME TOP_i/Timing/clk_wiz_0/inst/CLK_CORE_DRP_I/clk_inst/mmcm_adv_inst NODELAY false OPROGRAMMING ORIG_CELL_NAME ORIG_REF_NAME PARENT TOP_i/Timing/clk_wiz_0/inst/CLK_CORE_DRP_I/clk_inst PBLOCK PHASESHIFT_MODE WAVEFORM POWER_OPTED_CE PRIMITIVE_COUNT 1 PRIMITIVE_GROUP CLK PRIMITIVE_LEVEL LEAF PRIMITIVE_SUBGROUP gclk PRIMITIVE_TYPE CLK.gclk.MMCME2_ADV PRSHELL_OK_FOR_IMPL false PRSHELL_SKIP_IP false PWR_MODE STD RAM_DECOMP power RAM_STYLE distributed REF_JITTER1 0.01 REF_JITTER2 0.01 REF_NAME MMCME2_ADV REG_TO_SRL false RETIMING_BACKWARD -1 RETIMING_FORWARD -1 REUSE_STATUS RLOC ROM_STYLE distributed RPM RPM_GRID GRID RW_ADDR_COLLISION true SDX_FEATURE_ROM false SETUP_SLACK 0.0 SEU_PROTECTED 0 SHREG_EXTRACT YES SIM_COLLISION_CHECK WARNING_ONLY SLR SLR_INDEX 0 SOFT_HLUTNM SRL_STYLE srl_reg SRL_TO_REG false SS_EN FALSE SS_MODE CENTER_HIGH SS_MOD_PERIOD 10000 STARTUP_WAIT false STATUS PLACED TRANSIENT_FILTER BYPASS USER_LAGUNA false USER_SLL_REG false USER_SLR_ASSIGNMENT USE_DSP NO USE_DSP48 NO USE_LUTNM true USE_RLOC true USE_TRACE_DATA_EDGE_DETECTOR 0 XBLKNM XILINX_LEGACY_PRIM XPM_CDC NONE XSTLIB false X_CORE_INFO srl_bus_name srl_name
07-20-2018 01:32 AM - edited 07-20-2018 02:07 AM
It seems to be an issue with combining Dynamic reconfiguration with the dynamic fine phase shift. When the AXI - reconfiguration is disabled, the phase shift works again.
I have found the following in XAPP888, but I think the meaning is somewhat unclear
Frequency, phase, and duty cycle can all be changed through the DRP port.
Fine-phase shifting is not allowed for the initial configuration or during reconfiguration.
My interpretation would be that the fine phase shifting is not allowed to be enabled in the initial configuration, but can later be enabled trough the DRP port, furthermore do not do any phase shifting during reconfiguration.
Then on the other hand nowhere in any application note or manual can I find the register which can be used to enable the fine phase shifting.
07-23-2018 05:13 PM
Hi @tlapauw,
You found the right information there. The Fine Phase Shift is not allowed / supported at any time, while also using the DRP function.
If you really need to use the DRP resources, you may have to use the Static Phase Shift instead, which is supported. Please not that the SPS has a coarser granularity, so you might not be able to achieve exactly the same phases you would with the DPS.
Thanks,