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Visitor
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Registered: ‎06-21-2018

MMCM glitchy clock passing through BUFGCE in simulation

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Hi, 

I am trying to instantiate BUFGCE in my clock tree to get clock gating behavior in design. The clock output from MMCM is connected to BUFGCE element as below.

clock_network2.jpg

 

When i try to simulate the design i see that during the initial phase of clock when MMCM does not give stable clock and when the enable to BUFGCE is disable the clock is still propagated.

clock_network_sim_1.jpg

 

hsmclk1 is output from BUFGCE element and it can be seen that the initial clock pulses are getting through. 

Is there a reason why this is so?

 

Regards,

Sumesh

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Visitor
Visitor
825 Views
Registered: ‎06-21-2018

Thanks a lot. 

How do i get the updated verilog model?

View solution in original post

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Moderator
Moderator
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Registered: ‎08-08-2017

Hi @sumeshpv

 

I have checked at this my end and observed the same behavior in behavioral Simulation. clk_out1 is output from MMCM and clk_out is output from BUFGCE.

 

Behavioral Simulation 

 

Capture.PNG

 

Post Synthesis functional and timing Simulation also shows the same behavior.

I will discuss it internally to check if we are missing something here.

meanwhile can you check this on hardware and let us know if same behavior is there.

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Moderator
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Registered: ‎04-18-2011
Hi guys,

It is worth taking a step back.
How is the CE pin controlled?
Is the mmcm lock used as part of the logic to control it?
Have you tried a simulation with no mmcm just try a bufgce and control its ce pin in the simulation see what occurs
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Moderator
Moderator
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Registered: ‎08-08-2017

Hi @klumsde and @sumeshpv

 

In the Current implementation the CE pin is assigned with Logic '0'.

 

With the Locked output from MMCM connected to CE input of BUFGCE, same behavior is observed.

 

Capture1.PNG

 

 

With only BUFGCE in the design and CE controlled through test bench, the behavior is not proper till 100ns . 

 

Capture2.PNG

 

So it looks to me that BUFGCE is passing the clock independent of CE input till 100ns and expected behavior is observed after 100ns. Seems to be BUFGCE modelling issue.

 

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Moderator
Moderator
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Registered: ‎08-08-2017

Hi Guys,

 

The Verilog Unisim model for BUFGCE is changed from VIVADO 2018.1 , so i have checked in VIVADO 2017.4, but same issue is observed.

 

Then checked the same implementation using target language as VHDL . It shows correct behavior

 

Capture4.PNG 

 

It is confirmed that there is issue in Verilog Unisim model. I will once again confirmed it internally and file change request to get it corrected.

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Visitor
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Registered: ‎06-21-2018

Thanks a lot. 

How do i get the updated verilog model?

View solution in original post

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