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Observer
Observer
16,331 Views
Registered: ‎10-17-2013

MMCM with smoothly varying output frequency?

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I want to achieve long-term synchronisation between two loosely coupled systems. The nominal frequency is fixed, but over time, normal tolerances can cause relative clock slips which I want to avoid. What I would like, therefore, is to be able to increase or decrease my local clock frequency by a very small amount (without any glitches), depending on whether a connecting FIFO is slowly filling or emptying.

 

In principle, the MMCM can do such a thing, because that's exactly what the spread-spectrum mode does. I just want to have direct control of the modulation rather than presetting a fixed pattern. Much study of UG472, XAPP888 and PG065 has not given me any idea of how it might be possible, though. Resetting the MMCM, reprogramming and then waiting for it to re-acquire lock is no good.

 

At present, I'm thinking that I might have to use two MMCMs so I can program one while the other runs, and roll my own phase comparator and switcher to change between them when they line up reasonably closely. That seems very inelegant, though :-(

 

Anyone know if what I want can be done?

 

TIA.

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Professor
Professor
30,619 Views
Registered: ‎08-14-2007

Actually phase shifting is very simple with the 7-series MMCM because you can just continue to increment or decrement and the phase automatically wraps.  So in effect a train of phase shift pulses can either speed up or slow down the clock depending on the UP/DOWN control of the phase shift logic.

-- Gabor

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Scholar
Scholar
16,325 Views
Registered: ‎02-27-2008

s,

 

Been there, done that:  not a good solution.

 

Yes, by placing a MMCM in a test mode (unsupported) you may take over the tap control, and use it as a programmable ring oscillator, but keeping it locked (to anything) and controling it while being able to adjust the frequency is not worth the effort.

 

The resulting jitter and phase noise, and short term wander makes it unusable.

 

You are much better off using a quartz crystal voltage controlled oscillator in a control loop implemented in the FPGA logic.

 

Another approach (if the required frequency is below 25 MHz or so) is to use a direct digital frequency synthesizer (also known as a phase accumulator).  The DDFS may have an arbitralily precise step (for example a 48 bit DDFS made from one DSP48 block yields a step size of ~3.5 E -15).

 

The jitter of a DDFS is one clock period of the DDFS clock.  The Fout = Clock * N / 2^M, where M = number of bits in the accumulator, and N is ythe phase constant (must be greater than or equal to 1/2 2^ M -- Fout must be less than 1/2 clock Fin).

 

If you use a DDFS with a FIFO, you do not need to process the output, but rather just use the MSB as the clock out to the FIFO.

 

https://encrypted.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact=8&ved=0ahUKEwiymsDvjM3KAhUKnoMKHX8zDb8QFggmMAE&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F4202402%2F4215983%2F04216005.pdf%3Farnumber%3D4216005&usg=AFQjCNGDG4O3M_P0...

 

(IEEE account needed)

 

 

 

 

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
16,321 Views
Registered: ‎10-11-2007

There isn't really a good way to do custom frequency modulations at the granularity you desire. 

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Explorer
Explorer
16,306 Views
Registered: ‎07-18-2011

I did this several years ago on a Virtex 2 Pro using its DCMs. I don't know if this will still work in the newer MMCMs. I was transmitting multiple streams of digitized analog video across a network. Analog video is sensitive to changes in frequency and phase so I needed something that provided very smooth adjustments to the clock. This sounds similar to your requirements. 

 

The basic idea is to slowly and consistently adjust the phase of the clock over time - which is essentially a change in frequency. I did this using the fine phase adjustment interface on the DCM. The phase adjustment interface works like a delay line with taps so you can only make so many adjustments. To get around this limitation I used two DCMs and muxed between them. When one DCM hit it's min/max phase adjustment I would switch over to the other DCM on the falling edge of the clock. As soon as one DCM became inactive it would quickly adjust its phase to the opposite side of the delay line.

 

Control logic monitored a fifo filled with video samples received from the network. If the fifo was filling up then the phase was adjusted to speed up the clock. If it was running low then the clock would slow down. It worked beautifully.

 

 

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Professor
Professor
30,620 Views
Registered: ‎08-14-2007

Actually phase shifting is very simple with the 7-series MMCM because you can just continue to increment or decrement and the phase automatically wraps.  So in effect a train of phase shift pulses can either speed up or slow down the clock depending on the UP/DOWN control of the phase shift logic.

-- Gabor

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Scholar
Scholar
16,294 Views
Registered: ‎02-27-2008

Gabor,


If that works, and you can wrap fast enough, what is the ppm +/- acheivable in frequency?

 

In the older devices, it was just too little.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Professor
Professor
16,278 Views
Registered: ‎08-14-2007

It's kind of a comlpicated formula.  The phase shift is based on the VCO cycle, so the number of steps to go one complete period of an output clock depends on the output divisor.  There are 56 steps per VCO clock period.  The clock that controls phase shifting can be quite fast, but you can only increment or decrement phase every 13 cycles if I read the data sheet correctly (PSDONE comes 12 cycles after PSINCDEC).  For Artix 7 the clock for this can be up to 550 MHz (higher speed grades) or 450 MHz (lower speed grades).  The VCO range for the lowest speed grade Artix-7 is 600 to 1200 MHz.  So as I see it the worst case would be running the VCO at 1200 MHz, then using 450 MHz as the PSCLK signal.  Then you can add or subtract one 1200 MHz VCO clock every 56 * 13 period of the PSCLK which amounts to every 1941+1/3 VCO clock periods.  That gives you about +/-515 ppm control.  Obviously you can do better with a higher speed grade part and using the lower end of the VCO range.

-- Gabor
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Scholar
Scholar
16,276 Views
Registered: ‎02-27-2008

Wow,

 

That is impressive, and useful.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer
Observer
16,268 Views
Registered: ‎10-17-2013

Ah, excellent!

 

I'd thought about something like that, but hadn't worked through it in detail and hadn't realised the phase would wrap - I thought it would just get stuck at the max/min point.

 

It does create a bit of jitter if I don't shift on every cycle (which would alter the frequency too much) but almost certainly nothing I can't live with.

 

Thanks!

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Newbie
Newbie
3,583 Views
Registered: ‎10-02-2017

this method, of using the MMCM to continuosly phase shift, is fantastic. i was looking for an answer on how to synchronize two systems for video transport. i am sending video data over a network and need to display it at the receiver end. i had been playing around with an idea similar to this, but the idea presented here is much more elegant. i've implemented a basic concept of this and it is working nicely in initial testing.

 

i have a fifo filling up from inbound video data. i have set a watermark level at the mid point of the fifio. when the fifo gets below the watermark (display video too fast) then i begin the phase shift process to slow the clock down. the fifo then fills up beyond the watermark and i return the phase shift back to zero. this has to be done very smoothly in order for avoid jumping timing on the monitor and causing a display glitch. so i've implemented a core that can adjust the phase every X clock cycles. For example, i run the phase adjuster (psen,pclk,psincdec,psdone) at 100mhz. it takes 13 cycles to increment the phase one step. i then have a microblaze adjustable "idle" period in 100mhz increments the microblaze is watching the fifo watermark and adjusting the "idle" period every frame to smoothly increase the rate at which the phase is being shifted. so this is kind of like a 2nd order filter of sorts, first step of the filter adjusts the phase every X clock cycles, and then the 2nd loop of the filter adjusts the value of X every frame. This is producing very very small increments or decrements in the clock rate of the video display core allowing it to fill back up with video data and produce a nice clean signal. this is working for SVGA and NTSC video transport.

 

this is such a great idea and one of the truely clever ways to use a feature in an fpga, thanks for presenting it here. 

any other tips or improvements? i'd love to hear :D

 

thanks

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Registered: ‎01-08-2012

@spanofle wrote:
any other tips or improvements? i'd love to hear :D

 

If you are using transceivers (GTX, etc.) the transmit output has phase interpolator that can be controlled to adjust the phase, in a similar way to the MMCM phase adjustment that Gabor suggested.

IIRC, for 7 series, you need to make the phase interpolator adjustment through DRP, but for Ultrascale and later, there's actually an interface that allows you to control a frequency offset directly (which will cause the phase shift to advance or retard continuously at the rate you request).  There are numerous app notes showing how to use this for various applications.

 

For my (not particularly cost-sensitive) designs though, I usually use an external PLL device such as the Si5347A from Silicon Labs when I want to lock to an external clock or data rate.  It has jitter performance much better than any FPGA.  There are similar parts available from several manufacturers.

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