03-14-2019 04:20 PM
Target device: Kintex7, xc7k325tffg676-2
Design contains a MMCME2_ADV configured with CLKIN1_PERIOD => 2.000 (500MHz). CLKIN1 source is a differential pair driven by an external DAC. Design meets timing.
What are the implications of driving the input clock from the DAC with a 250MHz clock or a 125MHz clock? Will the MMCM operate correctly? Are there any issues locking to a lower frequency than the MMCM is configured for?
03-15-2019 06:08 AM
Welcome to the Xilinx Forum!
For your speed-grade 2 Kintex-7, Table 41 in Xilinx document DS182 indicates the MMCM maximum input frequency is at least 800MHz, and the minimum input frequency is 10MHz. Table 41 also shows that the MMCM maximum output frequency is at least 800MHz and the minimum output frequency is 4.69MHz (using CLKOUT4_CASCADE reduces this to 0.036MHz).
What are the implications of driving the input clock from the DAC with a 250MHz clock or a 125MHz clock? Will the MMCM operate correctly?
Based on MMCM specifications from DS182, the MMCM will easily “lock” (as you say) to a clock input of 250MHz or 125MHz. -but, I am a little confused by your questions. You say “driving the input clock from the DAC”. Typically, for a source-synchronous interface between the FPGA and a DAC, it is the MMCM in the FPGA that sends a data-clock to the DAC. Is this what you are doing?
03-15-2019 01:26 PM
Yes, FPGA=>DAC interfaces are typically source synchronous but this design is atypical. It is system synchronous with the DAC providing the data clock to the FPGA.
We want to explore the system behavior when the data clock from the DAC is reduced from 500MHz to either 250MHz or 125MHz. We want to see the effect on the system of reducing the sample rate of the DAC. But I want to make sure that the MMCM will operate correctly at the lower frequencies if it has been configured for a 500MHz input clock (CLKIN1_PERIOD => 2.000).
03-15-2019 05:21 PM - edited 03-15-2019 05:37 PM
Thanks for further describing your work. System synchronous interfaces can be challenging. It is amazing that you had this one working at 500MHz!
In short, the MMCM can accept a clock input at either 500MHz, 250MHz or 125MHz – and output a clock of the same frequency that you can use for clocking the LVDS data out of the FPGA. Everything will work fine if you tell the MMCM the exact frequency of the input and output clock using the Clocking Wizard as described in Xilinx document PG065.
If you tell the MMCM that the input and output clock frequency is 500MHz – but instead send it an input clock with a frequency that is not 500MHz then the MMCM may not work properly (because some of the internal frequency limitations of the MMCM may be exceeded). Further, using an MMCM input clock frequency other than the frequency specified in the Clocking Wizard will cause both timing constraints and timing analysis to be incorrect. However, if the MMCM internal frequency limitations are not exceeded (and despite the incorrect timing analysis), the FPGA to DAC interface may physically work - but this requires further study.
03-15-2019 05:37 PM
Paragraph two above does not describe what I want to do. Paragraph three does.
I want to build an MMCM to run at 500MHz. I want to change the input clock to either 250MHz or 125MHz clock without re-building the MMCM. The input frequency change needs to be done at the DAC without re-configuring the FPGA.
You are saying that this may not work properly because of some internal MMCM issues. That is what I was afraid of.
However, I don’t think that timing analysis should be affected. If the design meets timing at the higher frequency, it should still meet timing at a lower frequency. Or am I missing something?
03-16-2019 04:14 AM
The procedure by which the MMCM creates an output clock from an input clock is described on about pages 72 and 76 of UG472. This procedure involves parameters, M=CLKFBOUT_MULT_F, D=DIVCLK_DIVIDE, O=CLKOUT_DIVIDE and the frequency, fVCO, of a VCO found inside the MMCM. As described in Table 41 of DS182, this VCO has a frequency range from 600MHz to at least 1200MHz for the Kintex-7. The challenge in what you are doing is to keep the VCO frequency in-range.
Instead of directly using the MMCM equations from UG472, you can use the Clocking Wizard itself to determine whether the VCO frequency stays in-range. On the “MMCM Settings” tab of the Wizard you will see the equation parameters from UG472. Start by configuring the MMCM for an input and output clock frequency of 500MHz – and note the settings that the Wizard selected for CLKFBOUT_MULT_F and DIVCLK_DIVIDE. Then, change the input/output clock frequency to 250MHz. Return to the “MMCM Settings” tab and check “Allow Override Mode”. Then, manually change CLKFBOUT_MULT_F and DIVCLK_DIVIDE back to the values you noted for the input/output clock frequency of 500MHz. The Wizard will then tell you if these setting result in an invalid VCO frequency. -which, I’m sorry to say, seems to be the case for what you are trying to do.
Perhaps you can fiddle with the Clocking Wizard in this way and get something that works for you. If you do, I hope you'll let us know via this thread.
03-16-2019 05:02 AM
Can you chang your fpga code a little ?
Instead of feeding the mmcm from the dac clock, to drive the output registers,
bring the clock in on an IO clock port, to drive the IO of the FPGA,
then in the FPGA, drive the output registers with a FIFO,
that way you have decoupled the fpga clock from the output clock,
Then "all" the FPGA has to do is keep the FIFO from emptying,
and the FPGA can run at a constant clock with an enable , such as the fifo almost empty flag,
03-25-2019 02:41 PM
Thanks to all who replied. The override mode of the Clocking Wizard looks promising but as markg pointed out, it will likely result in an invalid VCO frequency. Starting with an input and output frequency of 500 MHz, I was able to get a valid VCO frequency for 250 MHz input/output clock frequencies but not 125 MHz. This gets me half of what I want which may be enough, I don’t know yet.
Another approach that I want to try but have not had the time to test is using two MMCMs. This assumes that one IBUFDS can drive more than one MMCM. I could not find any restrictions in any of the data sheets or user guides. If anyone knows whether or not this will work, please comment. The drawing below shows the circuit.
03-26-2019 06:08 AM
This assumes that one IBUFDS can drive more than one MMCM.
You’ll need to route the clock from the IBUFDS through a clock buffer (eg. BUFR or BUFG) in order to reach two MMCMs.
I think that drjohnsmith has given you a good approach to this problem. However, like the Oracle of Delphi, his descriptions sometimes need a little interpretation :-) I think he is suggesting that you get a constant 500MHz clock, CLK500, from another MMCM in your design. CLK500 is used to keep a FIFO full of data that will eventually be sent to the DAC. The clock, CLKD, coming from the DAC is routed through a clock-capable pin on the FPGA and into a clock buffer (not an MMCM) in order to place CLKD in the FPGA clock-tree. CLKD is used to clock data out of the FIFO and to send this data to the DAC. As drjohnsmith says, the only job of CLK500 is to keep the FIFO full of data. Further, since CLKD does not go through an MMCM, you avoid the VCO-out-of-range problem. Finally, the FIFO is a good way handle the CLK500-to-CLKD clock-crossing.
03-26-2019 06:18 PM
Thanks Mark, adding a BUFG to the input clock sounds like the least disruptive solution to me. I inherited this design and I hesitate to make drastic changes for fear of breaking something.
The FIFO approach sounds like a good idea but the outputs to the DAC are SERDES in 4:1 DDR mode. Adding FIFOs to the path may complicate the routing too much. And to further complexicate the issue, I need an MMCM for phase shifting of the DAC clock to meet timing on the outputs to the DAC.
03-28-2019 02:38 AM
Yep - that's a pretty slick idea.
Then one can just use BUFIO/BUFR (if I'm following correctly) to drive the FIFO read -> to output serial modules.