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Observer okgultekin_44
Observer
226 Views
Registered: ‎01-15-2019

MMCME3 CLOCKOUT ISSUE

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Hello everyone,

I have an MMCME3 primitive that have several output clocks.

Ex.

 MMCME3_BASE_inst     : MMCME3_BASE
   generic map (
      BANDWIDTH          => "OPTIMIZED",           -- Jitter programming (HIGH, LOW, OPTIMIZED)
      CLKFBOUT_MULT_F    => 4.0,                   -- Multiply value for all CLKOUT (2.000-64.000)
      CLKFBOUT_PHASE     => 0.0,                   -- Phase offset in degrees of CLKFB (-360.000-360.000)
      CLKIN1_PERIOD      => 2.5,                 -- Input clock period in ns units, ps resolution (i.e. 33.333 is 30 MHz).
      CLKOUT0_DIVIDE_F   => 2.0,                   -- Divide amount for CLKOUT0 (1.000-128.000)
      -- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
      CLKOUT0_DUTY_CYCLE => 0.5,
      CLKOUT1_DUTY_CYCLE => 0.5,
      CLKOUT2_DUTY_CYCLE => 0.5,
      -- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
      CLKOUT0_PHASE      => 0.0,
      CLKOUT1_PHASE      => 0.0,
      CLKOUT2_PHASE      => 0.0,
      -- CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
      CLKOUT1_DIVIDE => 2,
      CLKOUT2_DIVIDE => 3,
      DIVCLK_DIVIDE      => 1,                     -- Master division value (1-106)
      -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
      REF_JITTER1        => 0.100                  -- Reference input jitter in UI (0.000-0.999)
   )
   port map (
      -- Clock Outputs outputs: User configurable clock outputs
      CLKOUT0            => s_rx_pllmmcm_div,     -- 1-bit output: CLKOUT0
      CLKOUT0B           => open,                  -- 1-bit output: Inverted CLKOUT0   
      -- Clock Outputs outputs: User configurable clock outputs
      CLKOUT1            => s_rx1_clkdiv,         -- 1-bit output: CLKOUT0
      CLKOUT1B           => open,                  -- 1-bit output: Inverted CLKOUT0   
      -- Clock Outputs outputs: User configurable clock outputs
      CLKOUT2            => s_rx2_clkdiv,         -- 1-bit output: CLKOUT0
      CLKOUT2B           => open,                  -- 1-bit output: Inverted CLKOUT0                 
      -- Feedback outputs: Clock feedback ports
      CLKFBOUT           => s_px_pllmmcm,          -- 1-bit output: Feedback clock
      CLKFBOUTB          => open,                  -- 1-bit output: Inverted CLKFBOUT
      -- Status Ports outputs: MMCM status ports
      LOCKED             => o_cmt_locked,          -- 1-bit output: LOCK
      -- Clock Inputs inputs: Clock input
      CLKIN1             => s_bitclk,              -- 1-bit input: Clock
      -- Control Ports inputs: MMCM control ports
      PWRDWN             => '0',                   -- 1-bit input: Power-down
      RST                => i_reset,               -- 1-bit input: Reset
      -- Feedback inputs: Clock feedback ports
      CLKFBIN            => o_px_clk               -- 1-bit input: Feedback clock
   );  
    -----------------------------------------------------------------------------
    -- Global Clock Buffers 0
    -----------------------------------------------------------------------------    
    BUFG0_FB_inst         : BUFG
    port map (
       O                 => o_rx1_clkdiv,          -- 1-bit output: Clock output
       I                 => s_rx1_clkdiv      -- 1-bit input: Clock input
    ); 
    
    -----------------------------------------------------------------------------
    -- Global Clock Buffers 1
    -----------------------------------------------------------------------------    
    BUFG1_FB_inst         : BUFG
    port map (
       O                 => o_rx2_clkdiv,          -- 1-bit output: Clock output
       I                 => s_rx2_clkdiv      -- 1-bit input: Clock input
    ); 
    
    -----------------------------------------------------------------------------
    -- Global Clock Buffers 2
    -----------------------------------------------------------------------------    
    BUFG2_FB_inst         : BUFG
    port map (
       O                 => o_rx_clkdiv,          -- 1-bit output: Clock output
       I                 => s_rx_pllmmcm_div      -- 1-bit input: Clock input
    );  

Input clock frequency is 65MHz which name is s_bitclk. I need 3 different clocks. Thats wyh, I used 2 clockout divider.

First clock output frequency is 130MHz. (s_rx_pllmmcm_div) 

Second clock output frequency should be 65 MHz because clock divided by 2 but unfortunately its still 130MHz.

Last one should be approximately 43.3 MHz but frequency changes between 80-90MHz. 

And also, second and third clock's amplitude and waveform are so weak than first clock output's amplitude. 

How can I configure mmcme3 to get several different clock?

 

yyi.gif

 

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Moderator
Moderator
141 Views
Registered: ‎04-18-2011

Re: MMCME3 CLOCKOUT ISSUE

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Hi @okgultekin_44

Is the Lock signal high. 

Reading the instantiation of the MMCM it seems like the input clock is not expected to be 65Mhz. 

input clock period is set to 2.5ns. So this is 400Mhz. 

The MMCM output can be calculated like so

FVCO = CLKIN *(M/D)

There is a requirement for the VCO frequency to be in a certain range. So the period of the input clock must be specified and the M and D settings need to be a specified range and satisfy the FVCO requirement for your specific device. 

After that the CLKOUTN_DIVIDE settings produce the output clocks. Only CLOCKOUT0 may use fractional division, the rest are integer division

The most foolproof way to do this is via the clocking wizard. 

I suspect that since you are not reflecting the real situation here (your parameters do no match) then your VCO is running out of spec. 

Use the clocking wizard here and you can't go too far wrong. 

Keith 

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2 Replies
Moderator
Moderator
142 Views
Registered: ‎04-18-2011

Re: MMCME3 CLOCKOUT ISSUE

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Hi @okgultekin_44

Is the Lock signal high. 

Reading the instantiation of the MMCM it seems like the input clock is not expected to be 65Mhz. 

input clock period is set to 2.5ns. So this is 400Mhz. 

The MMCM output can be calculated like so

FVCO = CLKIN *(M/D)

There is a requirement for the VCO frequency to be in a certain range. So the period of the input clock must be specified and the M and D settings need to be a specified range and satisfy the FVCO requirement for your specific device. 

After that the CLKOUTN_DIVIDE settings produce the output clocks. Only CLOCKOUT0 may use fractional division, the rest are integer division

The most foolproof way to do this is via the clocking wizard. 

I suspect that since you are not reflecting the real situation here (your parameters do no match) then your VCO is running out of spec. 

Use the clocking wizard here and you can't go too far wrong. 

Keith 

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-------------------------------------------------------------------------

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Historian
Historian
129 Views
Registered: ‎01-23-2009

Re: MMCME3 CLOCKOUT ISSUE

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Where did you come up with these multipliers and dividers?

The MMCM has a number of requirements that must be met in order for the MMCM to operate correctly and lock. One of them (as an example) is that the VCO frequency has to be in a defined range - for the Kintex UltraScale in a -2 speed grade, for example, it must be between 600MHz and 1440MHz (see DS892 Table 36).

The VCO frequency is determined by this formula   fVCO = fIN*CLKFBOUT_MULT_F/CLKOUT0_DIVIDE, so given your setup (fIN=65MHz, CLKFBOUT_MULT_F=4, CLKOUT0_DIVIDE), your VCO is (trying to) run at 130MHz - this is WAY WAY below the legal limit for the MMCM, and hence the MMCM is almost certainly not locking (and hence the outputs are invalid).

The correct way to determine the multipliers and dividers is to use the clocking wizard - that will always choose correct values for the multiplier and dividers that meet your requirements (the input and output frequencies that you want) while keeping all MMCM parameters (including fVCO) within their legal range (in fact, at their "optimal" values).

Avrum

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