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Adventurer
Adventurer
318 Views
Registered: ‎11-20-2018

Making differential clock signal.

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Hi. I', using xcku025-ffva-1156 (ultrascale + FPGA)

I am referring to application notes provided by xilinx.

I am going to use the reference code provided in xapp1315.

In this reference code, an external clock of 100 MHz enters to FPGA, passes IBUFDS_DIFF_OUT, and then goes to idelaye3.

image.png

I am going to design my top file containing this logic as shown in the picture below

The reference code  should receive 100 MHZ external clocks (go to IBUFDS), but my top design has only 50 MHZ external clocks.

image.png

What's the best way to solve a case like this?

The way I thought about it was to insert mmcm,  I'm not sure if the IDELAYE3 works differently, but the results didn't come out well.

image.png

Thanks.

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Moderator
Moderator
266 Views
Registered: ‎08-08-2017

Re: Making differential clock signal.

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Hi @kangsungsik 

This is already answered on your similar post

https://forums.xilinx.com/t5/Versal-and-UltraScale/IDATAIN-vs-DATAIN-in-IDELAYE3-input-port-xapp1315/m-p/1075724#M13277

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Moderator
Moderator
267 Views
Registered: ‎08-08-2017

Re: Making differential clock signal.

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Hi @kangsungsik 

This is already answered on your similar post

https://forums.xilinx.com/t5/Versal-and-UltraScale/IDATAIN-vs-DATAIN-in-IDELAYE3-input-port-xapp1315/m-p/1075724#M13277

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Making differential clock signal.

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Why do you want a differential clock inside the FPGA ?
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Adventurer
Adventurer
202 Views
Registered: ‎11-20-2018

Re: Making differential clock signal.

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Hi. @drjohnsmith 

The reason is because I want to use xapp1315 as a sub module in my design.

And it is because in xapp1315, the external clock passes IBUFDS_DIFF_OUT and both positive and negative are used.