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Adventurer
Adventurer
349 Views
Registered: ‎05-15-2014

Maximum safe transition time for Virtex 7 FPGA input signals

Hello

 

For Virtex-7 family, what is the maximum safe signal transition time for general inputs?

We could not find any information in Virtex-7 datasheet.

 

We have an input signal with slow rise time and fall time such as 10uS.

We don’t want to damage the FPGA with this signal since it remains in CMOS threshold region (0.63V to 1.17V) for a considerable time.

 

Best regards

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1 Reply
Moderator
Moderator
333 Views
Registered: ‎04-18-2011

Re: Maximum safe transition time for Virtex 7 FPGA input signals

You won't damage the FPGA in this case. 

We don't specify transition times for the inputs. particularly we don't give a maximum. 

This represents an endorsement of bad design practice. 

Signals should have good fast transition times. 

slow rise times mean that the signal is close to  and between the thresholds for longer. This makes them susceptible to noise.

 

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