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Visitor
Visitor
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Registered: ‎05-30-2016

Multi Region Clock - use of BUFG - xc7a100tifgg484-1L

Hey,

i have a clock issue with my Artix-7 (xc7a100tifgg484-1L) mounted on a carrier board (Both Trenz Electronic Model TE0703 and TE0712)

 

I want to do some basic programming and lit the LEDs on the carrierboard. As referred to my documents the LEDs goes to pin J16 and M17.

The clock signal is generated by a clock generator (Silicon Labs Si5338) and the output clock signal goes to pin E6 (clk_p) and F7 (clk_n).

For now i only use clk_p ( i red it is possible to only use the clk_p of a differential clock).

 

My constraints file:

set_property PACKAGE_PIN J16 [get_ports LED1]
set_property PACKAGE_PIN M17 [get_ports LED2]
set_property IOSTANDARD LVCMOS33 [get_ports LED2]
set_property IOSTANDARD LVCMOS33 [get_ports LED1]

create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports MGT_CLK0_P]

set_property PACKAGE_PIN F6 [get_ports MGT_CLK0_P]

my vhdl file:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity blinki is
    Port ( LED1       : out STD_LOGIC;
           LED2       : out STD_LOGIC;
           MGT_CLK0_P : in  STD_LOGIC);
end blinki;

architecture Behavioral of blinki is

signal counter : Integer;
begin
blink : process(MGT_CLK0_P,counter)
    begin  
    If rising_edge(MGT_CLK0_P) then
        counter <= counter + 1;
    end If;
    If counter = 12500000 then
        LED1 <= '1';
        LED2 <= '1';
    end If;
    If counter = 25000000 then
        LED1 <= '0';
        LED2 <= '0';
        counter <= 0;
    end If;    
end process blink;
end Behavioral;

If i try to generate the bitstream i get this error:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets MGT_CLK0_P_IBUF] >

    MGT_CLK0_P_IBUF_inst (IBUF.O) is locked to IPAD_X1Y44
     and MGT_CLK0_P_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

Ive watched the whole tutorial video on clocking and try to red the "ug472_7Series_Clocking" User Guide but i dont understand it.

 

I think the problem is that i go into Bank 216 (MGT)(Clock Region X1Y3) with my clock signal but have to pass it to Bank 15 (Clock Region X0Y2) with the use of the BUFG ?

 

Thanks, Björn

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Teacher
Teacher
5,710 Views
Registered: ‎03-31-2012

firstly Si5338 generates only differential clock so you have to use it as a differential clock source. You can't use it just the _p.
Secondly I don't think you can access the MGT reference clock pins directly, they're dedicated to the MGT block. I think there might be a way to configure the MGT block to forward the clock to the fabric.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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