Hello,
I have a design with a main 300 MHz clock and several clock enables that require correct multicycle constraint delay settings to be placed (else the design will fail timing). I read multiple Xilinx documents on how to do that and they weren't that clear. A xilinx FAE sent me an alternate format that also didn't work initially but he later modified it and now it does. This is an example of his format:
set my_ena_x1 [get_nets -of_objects [get_pins -of_objects [get_cells upconvert_qam_x8_inst/master_timing_inst/ena_1x_reg] -filter { DIRECTION == OUT }]]
set my_ena_x1_pins [get_pins -leaf -filter {IS_ENABLE} -of $my_ena_x1]
set my_ena_x1_cells [get_cells -of $my_ena_x1_pins]
set my_ena_x1_clocks [get_pins -leaf -filter {IS_CLOCK} -of $my_ena_x1_cells]
set_multicycle_path -from $my_ena_x1_clocks -to $my_ena_x1_cells -setup 32
set_multicycle_path -from $my_ena_x1_clocks -to $my_ena_x1_cells -hold 31
One of my enables goes into a VHDL module where it is used to generate another enable at the same rate. However I think the proper timing contraints aren't being applied to that because I get timing violations in the timing report in that module where the setup requirement is 3.3s which corresponds to source clock period. I know for a fact that the requirement should be that times 16 if the settings were applied correctly. Can someone explain how to extract that net to apply the timing setting correctly EVERYWHERE that enable goes?
I am still confused on the difference between nets and cells. Can someone also explain? I need to master this.
