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Observer
Observer
9,551 Views
Registered: ‎07-15-2015

Multiple clock gating - Unroutable Placement Errors

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I'm having a problem which I can't solve for days now, although it doesn't seem to be such a tricky one. So I decided to ask here for some input. I'm using the ISE Design Suite 14.7.

I'm basically trying to switch on and off multiple clocks and output them from my design for a Kintex-7 XC7K325T.
The first step is a PLL. From the board clock it generates the clock which will be gated as well as a second clock which will be output directly.

The second step consists of multiple (six) BUFGCE elements which should do the clock gating. They all have the same input clock (from the aforementioned PLL), but individual enable signals.

Additionally there is a second PLL stage with the same input clock as the BUFGCEs (this PLL will be dynamically reconfigurable, that's why I need the second PLL). Finally its output again is clock gated by a BUFGCE and another enable signal.

I simplified my design to the following code:

 

----------------------------------------------------------------------------------
--                                LIBRARIES                                     --
----------------------------------------------------------------------------------
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use UNISIM.vcomponents.all;


----------------------------------------------------------------------------------
--                               ARCHITECTURE                                   --
----------------------------------------------------------------------------------

architecture beh of top is

	signal global_board_clk			: std_logic;
	signal signal_reset			: std_logic;
	signal signal_PISO_PLL_locked		: std_logic;
	signal signal_controller_clk		: std_logic;
	signal signal_asic_clk			: std_logic;
	signal signal_locked			: std_logic;


	component PISO_clk
		port
		(
			-- Clock in ports
			CLK_IN1_P			: in std_logic;
			CLK_IN1_N			: in std_logic;
			-- Clock out ports
			CLK_OUT1			: out	std_logic;
			cntrl_clk			: out	std_logic;
			-- Status and control signals
			RESET				: in	std_logic;
			LOCKED				: out	std_logic
		);
	end component;

	component dummy_measurement_PLL
		port
		(
			CLK_IN1		: in std_logic;
			CLK_OUT1	: out std_logic;
			RESET		: in std_logic;
			LOCKED		: out std_logic
		);
	end component;

begin

	signal_reset <= not reset;	-- needs to be like this because of the reset button hardware


-- the PLL generates one direct output clock (CLK_OUT1) and one clock which will be gated (cntrl_clk)
	PISO_clk_PLL : PISO_clk
	port map
	(
		CLK_IN1_P	=> clk_p,
		CLK_IN1_N	=> clk_n,
		CLK_OUT1	=> delayed_PLL,	
		cntrl_clk	=> signal_controller_clk,
		RESET		=> reset,
		LOCKED		=> signal_PISO_PLL_locked
	);

	BUFG_sys_clock : BUFG 
	port map
	(
		O => global_board_clk,
		I => signal_controller_clk
	);

	
-- Clock gating buffers...

-- inst25
	BUFGCE_inst25 : BUFGCE
	port map
	(
		I				=> global_board_clk,	-- common PISO clock
		CE				=> PISO25_clk_enable,	-- PISO110 clock enable
		O				=> asic_piso_clk25	-- PISO110 clock output
	);
	
-- inst30
	BUFGCE_inst30 : BUFGCE
	port map
	(
		I				=> global_board_clk,	-- common PISO clock
		CE				=> PISO30_clk_enable,	-- PISO110 clock enable
		O				=> asic_piso_clk30	-- PISO110 clock output
	);
	
-- inst55
	BUFGCE_inst55 : BUFGCE
	port map
	(
		I				=> global_board_clk,	-- common PISO clock
		CE				=> PISO55_clk_enable,	-- PISO110 clock enable
		O				=> asic_piso_clk55	-- PISO110 clock output
	);

-- inst75
	BUFGCE_inst75 : BUFGCE
	port map
	(
		I				=> global_board_clk,	-- common PISO clock
		CE				=> PISO75_clk_enable,	-- PISO110 clock enable
		O				=> asic_piso_clk75	-- PISO110 clock output
	);
	
-- inst84
	BUFGCE_inst84 : BUFGCE
	port map
	(
		I				=> global_board_clk,	-- common PISO clock
		CE				=> PISO84_clk_enable,	-- PISO84 clock enable
		O				=> asic_piso_clk84	-- PISO84 clock output
	);
	
-- inst110
	BUFGCE_inst110 : BUFGCE
	port map
	(
		I				=> global_board_clk,	-- common PISO clock
		CE				=> PISO110_clk_enable,	-- PISO110 clock enable
		O				=> asic_piso_clk110	-- PISO110 clock output
	);



	m_dummy_PLL : dummy_measurement_PLL
	port map
	(
		CLK_IN1 => global_board_clk,
		CLK_OUT1 => signal_asic_clk,
		RESET => signal_reset,
		LOCKED => signal_locked
	);
 
 
-- buffer for measurement clock:
	BUFGCE_inst : BUFGCE
	port map
	(
		I				=> signal_asic_clk,		-- traget circuit base clock
		CE				=> Tar_clk_enable,		-- target circuit enable
		O				=> asic_Tar_clk			-- final target circuit clock signal
	);


end architecture beh;


Sythesis is fine, but at the implementation I get the following errors:

 

"ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
   pair have been found that are not placed at a routable site pair. The driver
   BUFGCTRL component <BUFG_sys_clock> is placed at site <BUFGCTRL_X0Y18>. The
   load BUFGCTRL component <BUFGCE_inst25> is placed at site <BUFGCTRL_X0Y29>.
   The BUFGCTRL components can use the fast path between them if they are placed
   in adjacent BUFGCTRL sites, and both are in the same half of the device (TOP
   or BOTTOM). You may want to analyze why this problem exists and correct it.
   This placement is UNROUTABLE in PAR and therefore, this error condition
   should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE
   constraint in the .ucf file to demote this message to a WARNING in order to
   generate an NCD file. This NCD file can then be used in FPGA Editor to debug
   the problem. A list of all the COMP.PINS used in this clock placement rule is
   listed below. These examples can be used directly in the .ucf file to demote
   this ERROR to a WARNING.
ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
   pair have been found that are not placed at a routable site pair. The driver
   BUFGCTRL component <BUFG_sys_clock> is placed at site <BUFGCTRL_X0Y18>. The
   load BUFGCTRL component <BUFGCE_inst55> is placed at site <BUFGCTRL_X0Y21>.
   The BUFGCTRL components can use the fast path between them if they are placed
   in adjacent BUFGCTRL sites, and both are in the same half of the device (TOP
   or BOTTOM). You may want to analyze why this problem exists and correct it.
   This placement is UNROUTABLE in PAR and therefore, this error condition
   should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE
   constraint in the .ucf file to demote this message to a WARNING in order to
   generate an NCD file. This NCD file can then be used in FPGA Editor to debug
   the problem. A list of all the COMP.PINS used in this clock placement rule is
   listed below. These examples can be used directly in the .ucf file to demote
   this ERROR to a WARNING.
ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
   pair have been found that are not placed at a routable site pair. The driver
   BUFGCTRL component <BUFG_sys_clock> is placed at site <BUFGCTRL_X0Y18>. The
   load BUFGCTRL component <BUFGCE_inst75> is placed at site <BUFGCTRL_X0Y26>.
   The BUFGCTRL components can use the fast path between them if they are placed
   in adjacent BUFGCTRL sites, and both are in the same half of the device (TOP
   or BOTTOM). You may want to analyze why this problem exists and correct it.
   This placement is UNROUTABLE in PAR and therefore, this error condition
   should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE
   constraint in the .ucf file to demote this message to a WARNING in order to
   generate an NCD file. This NCD file can then be used in FPGA Editor to debug
   the problem. A list of all the COMP.PINS used in this clock placement rule is
   listed below. These examples can be used directly in the .ucf file to demote
   this ERROR to a WARNING.
ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
   pair have been found that are not placed at a routable site pair. The driver
   BUFGCTRL component <BUFG_sys_clock> is placed at site <BUFGCTRL_X0Y18>. The
   load BUFGCTRL component <BUFGCE_inst84> is placed at site <BUFGCTRL_X0Y9>.
   The BUFGCTRL components can use the fast path between them if they are placed
   in adjacent BUFGCTRL sites, and both are in the same half of the device (TOP
   or BOTTOM). You may want to analyze why this problem exists and correct it.
   This placement is UNROUTABLE in PAR and therefore, this error condition
   should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE
   constraint in the .ucf file to demote this message to a WARNING in order to
   generate an NCD file. This NCD file can then be used in FPGA Editor to debug
   the problem. A list of all the COMP.PINS used in this clock placement rule is
   listed below. These examples can be used directly in the .ucf file to demote
   this ERROR to a WARNING.
ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
   pair have been found that are not placed at a routable site pair. The driver
   BUFGCTRL component <BUFG_sys_clock> is placed at site <BUFGCTRL_X0Y18>. The
   load BUFGCTRL component <BUFGCE_inst110> is placed at site <BUFGCTRL_X0Y30>.
   The BUFGCTRL components can use the fast path between them if they are placed
   in adjacent BUFGCTRL sites, and both are in the same half of the device (TOP
   or BOTTOM). You may want to analyze why this problem exists and correct it.
   This placement is UNROUTABLE in PAR and therefore, this error condition
   should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE
   constraint in the .ucf file to demote this message to a WARNING in order to
   generate an NCD file. This NCD file can then be used in FPGA Editor to debug
   the problem. A list of all the COMP.PINS used in this clock placement rule is
   listed below. These examples can be used directly in the .ucf file to demote
   this ERROR to a WARNING.
ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
   pair have been found that are not placed at a routable site pair. The driver
   BUFGCTRL component <PISO_clk_PLL/clkout2_buf> is placed at site
   <BUFGCTRL_X0Y7>. The load BUFGCTRL component <BUFG_sys_clock> is placed at
   site <BUFGCTRL_X0Y18>. The BUFGCTRL components can use the fast path between
   them if they are placed in adjacent BUFGCTRL sites, and both are in the same
   half of the device (TOP or BOTTOM). You may want to analyze why this problem
   exists and correct it. This placement is UNROUTABLE in PAR and therefore,
   this error condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error."

 

I expected BUFG output signals to be available globally and hence in all sites.

The link http://www.xilinx.com/support/answers/43637.html
suggests to constrain the location of the BUFGCTRLs to force them to adjacent sites.
So I tried this. It seems to work fine to constrain the "BUFG_sys_clock" and one of the "BUFGCE_inst" objects.
But any attempts of constraining more objects failed. (Pack:2811 Errors and again Place:1131)

(What makes somehow sense, I guess I cannot have seven adjacent sites.)

"The BUFGCTRL components can use the fast path between them if they are placed in adjacent BUFGCTRL sites, and both are in the same half of the device (TOP or BOTTOM)."
Does that mean I can only drive the two BUFGCEs of the neighbouring sites of the PLL? Not more?
Is there a way to gate a clock with more enable signals? (I could of course build some clock gating in a logic block, but I can't imagine that's the best solution.)

Is there a general problem with my strategy of solving the task or do I just try to constrain the locations in a wrong way?

I also found the hint to set an environment variable to demote the error to a warning. If I do this, the implement step works fine. However I'd rather like to understand and solve the actual problem than ignore it.
(http://www.xilinx.com/support/answers/34346.html)

I'd appreciate your help,
asteric.

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Highlighted
Xilinx Employee
Xilinx Employee
17,685 Views
Registered: ‎09-20-2012

Re: Multiple clock gating - Unroutable Placement Errors

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Hi @asteric_

Are you using clocking wizard IP?

 

If yes, then disable buffer insertion on PLL/MMCM outputs as you already have buffers instantiated in code.

 

Capture.PNG

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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View solution in original post

7 Replies
Highlighted
Xilinx Employee
Xilinx Employee
9,537 Views
Registered: ‎09-20-2012

Re: Multiple clock gating - Unroutable Placement Errors

Jump to solution

Hi @asteric_

 

Can you try removing this BUFG_sys_clock? 

 

BUFG_sys_clock : BUFG 
	port map
	(
		O => global_board_clk,
		I => signal_controller_clk
	);

 Why are you cascading PLL's?

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Observer
Observer
9,454 Views
Registered: ‎07-15-2015

Re: Multiple clock gating - Unroutable Placement Errors

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Thanks a lot for your reply.

 

I need the cascaded PLLs, because the second one is a reconfigurable PLL. This isn't obvious in the example code, because I wanted to keep it simple.

I tried to remove the buffer, but the errors stay. Only the PISO_clk_PLL/clkout2_buf is now mentioned instead of the BUFG_sys_clock of course.

 

Best regards.

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Xilinx Employee
Xilinx Employee
9,438 Views
Registered: ‎09-20-2012

Re: Multiple clock gating - Unroutable Placement Errors

Jump to solution

Hi @asteric_

 

Please post the new error messages.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Observer
Observer
9,379 Views
Registered: ‎07-15-2015

Re: Multiple clock gating - Unroutable Placement Errors

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Sure.

I just changed

        cntrl_clk    => signal_controller_clk,

to
        cntrl_clk    => global_board_clk,

and removed the BUFG_sys_clock.


The error messages are now as follows:

 

ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
   pair have been found that are not placed at a routable site pair. The driver
   BUFGCTRL component <PISO_clk_PLL/clkout2_buf> is placed at site
   <BUFGCTRL_X0Y8>. The load BUFGCTRL component <m_dummy_PLL/clkin1_buf> is
   placed at site <BUFGCTRL_X0Y23>. The BUFGCTRL components can use the fast
   path between them if they are placed in adjacent BUFGCTRL sites, and both are
   in the same half of the device (TOP or BOTTOM). You may want to analyze why
   this problem exists and correct it. This placement is UNROUTABLE in PAR and
   therefore, this error condition should be fixed in your design. You may use
   the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message
   to a WARNING in order to generate an NCD file. This NCD file can then be used
   in FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
   pair have been found that are not placed at a routable site pair. The driver
   BUFGCTRL component <PISO_clk_PLL/clkout2_buf> is placed at site
   <BUFGCTRL_X0Y8>. The load BUFGCTRL component <BUFGCE_inst30> is placed at
   site <BUFGCTRL_X0Y12>. The BUFGCTRL components can use the fast path between
   them if they are placed in adjacent BUFGCTRL sites, and both are in the same
   half of the device (TOP or BOTTOM). You may want to analyze why this problem
   exists and correct it. This placement is UNROUTABLE in PAR and therefore,
   this error condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
   pair have been found that are not placed at a routable site pair. The driver
   BUFGCTRL component <PISO_clk_PLL/clkout2_buf> is placed at site
   <BUFGCTRL_X0Y8>. The load BUFGCTRL component <BUFGCE_inst55> is placed at
   site <BUFGCTRL_X0Y20>. The BUFGCTRL components can use the fast path between
   them if they are placed in adjacent BUFGCTRL sites, and both are in the same
   half of the device (TOP or BOTTOM). You may want to analyze why this problem
   exists and correct it. This placement is UNROUTABLE in PAR and therefore,
   this error condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
   pair have been found that are not placed at a routable site pair. The driver
   BUFGCTRL component <PISO_clk_PLL/clkout2_buf> is placed at site
   <BUFGCTRL_X0Y8>. The load BUFGCTRL component <BUFGCE_inst75> is placed at
   site <BUFGCTRL_X0Y26>. The BUFGCTRL components can use the fast path between
   them if they are placed in adjacent BUFGCTRL sites, and both are in the same
   half of the device (TOP or BOTTOM). You may want to analyze why this problem
   exists and correct it. This placement is UNROUTABLE in PAR and therefore,
   this error condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
   pair have been found that are not placed at a routable site pair. The driver
   BUFGCTRL component <PISO_clk_PLL/clkout2_buf> is placed at site
   <BUFGCTRL_X0Y8>. The load BUFGCTRL component <BUFGCE_inst84> is placed at
   site <BUFGCTRL_X0Y2>. The BUFGCTRL components can use the fast path between
   them if they are placed in adjacent BUFGCTRL sites, and both are in the same
   half of the device (TOP or BOTTOM). You may want to analyze why this problem
   exists and correct it. This placement is UNROUTABLE in PAR and therefore,
   this error condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

Thank you for your help.

 

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Highlighted
Xilinx Employee
Xilinx Employee
17,686 Views
Registered: ‎09-20-2012

Re: Multiple clock gating - Unroutable Placement Errors

Jump to solution

Hi @asteric_

Are you using clocking wizard IP?

 

If yes, then disable buffer insertion on PLL/MMCM outputs as you already have buffers instantiated in code.

 

Capture.PNG

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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View solution in original post

Highlighted
Observer
Observer
9,127 Views
Registered: ‎07-15-2015

Re: Multiple clock gating - Unroutable Placement Errors

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Hi Deepika.

 

I changed the buffer as in the screenshot and the error disappeared. Although I'm not sure why the buffer was a problem. Could you maybe explain what happened, so I don't fall over this buffer-mix-up again?

 

Anyway thank you a lot for your help! :-)

 

asteric

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Xilinx Employee
Xilinx Employee
9,105 Views
Registered: ‎09-20-2012

Re: Multiple clock gating - Unroutable Placement Errors

Jump to solution

Hi @asteric_

 

Glad to know that it helped.

 

You had an additional BUFG on the MMCM output path which is not needed as you are anyways driving this output to BUFGCE. This additional BUFG was causing the cascading problem.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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