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Registered: ‎04-26-2019

Multiple region BUFR alignment

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Hello,

I try to implement multiple region BUFR alignment (over two banks) following the description in UG472:

multiple_region_buffer_topology.png

My question concern the BUFR alignment circuit. My MRCC input clock can runs up to 625 MHz.
Does the alignment circuit need to run at this frequency ? (The documentation says that all BUFR CLR signals must be released synchronously with the high speed input clock but there is no description of how to implement this circuit to operate properly)

 

 

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Registered: ‎01-22-2015

@nicolas 

@avrumw and I believe that the BUFR Alignment procedure described on pg110 of UG472(v1.14) is incorrect.  Further, Vivado simulation shows that the stated procedure sometimes fails to align the BUFRs.

The BUFR Alignment procedure should be:

  • Set CE=0 on the BUFMRCE and wait a few cycles of clock input to the BUFMRCE
  • Set CLR=1 on all the BUFR and wait a few cycles of clock...
  • Set CLR=0 on all the BUFR and wait a few cycles of clock...
  • Set CE=1 on the BUFMRCE

As Avrum pointed out to me, this new BUFR Alignment procedure is implied by wording below Figure A-5 in UG472 and by wording on pg282 of UG953(v2019.1).

Mark

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Registered: ‎01-22-2015

@nicolas 

@avrumw and I believe that the BUFR Alignment procedure described on pg110 of UG472(v1.14) is incorrect.  Further, Vivado simulation shows that the stated procedure sometimes fails to align the BUFRs.

The BUFR Alignment procedure should be:

  • Set CE=0 on the BUFMRCE and wait a few cycles of clock input to the BUFMRCE
  • Set CLR=1 on all the BUFR and wait a few cycles of clock...
  • Set CLR=0 on all the BUFR and wait a few cycles of clock...
  • Set CE=1 on the BUFMRCE

As Avrum pointed out to me, this new BUFR Alignment procedure is implied by wording below Figure A-5 in UG472 and by wording on pg282 of UG953(v2019.1).

Mark

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Registered: ‎04-26-2019

Thank you for your answer markg@prosensing.com .
Indeed the sequence that you describes make more sense to me too.

Just to make sure I understand the same thing as you, you mention:

  • Set CLR=1 on all the BUFR and wait a few cycles of clock...
  • Set CLR=0 on all the BUFR and wait a few cycles of clock...

At this time, there is no clock on the input of BUFRs because the BUFMRCE is not enabled.
Are you talking about the clock on the input of BUFMRCE ?

Nicolas.

 

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Registered: ‎01-22-2015

Hi Nicolas,

As shown in Table 2-7 of UG472, the CLR of BUFR is an asynchronous input.  So, my "wait a few clock cycles" comment is not really necessary.  You can control CLR of the BUFR with HDL that operates in the domain of the clock-input to the BUFMRCE.  

You say the input to the BUFMRCE can be as high as 625MHz.  In the datasheet for your device, please check that 625MHz does not exceed Fmax for BUFMR, BUFIO, and BUFR.  Vivado timing analysis should warn you with "pulse-width" negative-slack if you try to exceed Fmax for these clock buffers.

Mark

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Registered: ‎04-26-2019

Hi Mark,

Yes the Fmax of BUFIO/BUFMR is 800MHz in my case. I use a VC707 (xc7vx485 speed grade -2).

Previously my BUFR alignment procedure was following the sequence described in UG472 p.110 and the BUFR were regularly unaligned.
My sequence was:

  • Set CE=0 on the BUFMRCE
  • Set CLR=1 on all the BUFR and wait a few cycles of clock...
  • Set CE=1 on the BUFMRCE and wait a few cycles of clock...
  • Set CLR=0 on all the BUFR

CE and CLR were controlled asynchronously of the high speed input clock, and I had set the CE_TYPE attribute of BUFMRCE to "ASYNC".

 

Now I changed the procedure according to the sequence that you proposed and also I changed the CE_TYPE to "SYNC" as @avrumw explained in the following thread:
https://forums.xilinx.com/t5/Implementation/BUFMRCE-CE-question/td-p/724141 

My acquisition path is now working and all BUFRs seems to be aligned everytime.

Thank you,
Nicolas.

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