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umi1992
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Registered: ‎11-22-2018

Multiplexing LVDS Outputs

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Hello there,

I am currenty trying to implement a design which uses the Spartan 6 OSERDES2 primitives to output data on LVDS transmission lines via OBUFDS.

I would like to be able to switch between LVDS Data coming from the outside and LVDS Data generated inside the FPGA. My Idea was now to just get the LVDS Data from the outside by IBUFDS and then instantiate a multiplexer to choose between this data and the one generated inside the device. The problem is now that i obviously can't put a multiplexer between the OSERDES2 primitives and the OBUFDS.

I have two additional ideas, but since I'm somewhat new in this field of engineering i was wondering if someone here could kindly evaluate these ideas or even offer me a better solution.

The first idea was to deserialize the LVDS data from outside using ISERDES2 primitives. this would give me the possibility to put the multiplexer infront of the OSERDES2.

The second idea would be to connect one lvds line to two i/o pins, one for the LVDS data from outside and one for the LVDS data generated inside. These pins would then be driven by OBUFTDS and depending on which of the signals should be active the corresponding OBUFTDS would be activated while the other one is getting set to high impedance state.

I hope i could somewhat cleary describe my problem and am looking forwards to your help.

 

 

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pthakare
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Registered: ‎08-08-2017

Hi @umi1992

Thanks for detail elaboration.

1. I dont find any issue with First approach.  In fact it is optimal than second approach as it is using only 2 IO pins (one differential pair)

Capture.PNG

2. For the second approach , It is using two differential pairs , how you will select P/N  input either two OBUFTDS blocks ?  is it implemented outside the FPGA?

 

Capture1.PNG

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pthakare
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Registered: ‎08-08-2017

Hi @umi1992

Apologies but I am not very clear with the multiplexer position in the design . It would be helpful if you share the

Schematic representation of your two approaches to validate.'

 

Best regards

Pramod Thakare

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umi1992
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Registered: ‎11-22-2018

Hi pthakare,

this first picture shows what I originally tried to do, but as i said i cant go from an OSERDES2 back to the logic creating a mux and then back to the output buffer, so this isn't working.

My first idea is now shown in the second picture which is probably the straight forward approach of deserializing the input data so it can be muxed before the OSERDES2. (not shown is the clocking that would have to be done)

The second idea shown in the third picture would be to use two i/o pins per lvds lane and making use of the obuftds buffers by putting one of the pins to high impedance depending on the state of 'sel'. 

 lvds_output_mux.jpglvds_output_mux_sol1.jpglvds_output_mux_sol2.jpg

I hope this helps you to understand my problem and to suggest an adequate solution for it.

Cheers.

pthakare
Moderator
Moderator
1,027 Views
Registered: ‎08-08-2017

Hi @umi1992

Thanks for detail elaboration.

1. I dont find any issue with First approach.  In fact it is optimal than second approach as it is using only 2 IO pins (one differential pair)

Capture.PNG

2. For the second approach , It is using two differential pairs , how you will select P/N  input either two OBUFTDS blocks ?  is it implemented outside the FPGA?

 

Capture1.PNG

----------------------------------------------------------------------------------------------------------------------------------------------

Reply if you have any queries, Give Kudos and accepts as Solution

-----------------------------------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post