11-06-2018 02:00 AM
I am using Zynq7000 SOC for a DSP emulation on FPGA (Artix7). I have an RTL from partner, who provided reference top1 which contains core of the processor along with the most common adjacent system level components such as reset synchronizer, debug module, AHB-Lite or AXI bridge. There is a top2 which encapsulates top1. Top2 is always used by reference test bench.
Note that signals to/from memories, i,e data RAM, Traceport etc. go between top1 and memory concerned. In other words they are not inputs or outputs of top2. With regards to other signals such as BReset, CLK, DRam0Lock0,JTMS, XOCDMode, BreakIn etc. are inputs or outputs of top2 but simply passed through to the top1 hierarchy.
I need to write a wrapper, which will fully instantiate all top level I/O properly terminated as per SoC requirements. Need to check for the local memory connectivity and system bus connections. Can some one help me to write this kind of wrapper? Any suitable resource which explains how to write this kind of wrapper will also helps. I need to connect the I/O signals appearing in top2 to FPGA wrapper such that FPGA wrapper drives various IOs appearing in top2. How to do that? Also what is the meaning of "top level I/O properly terminated as per SoC requirements" means?
11-06-2018 02:11 AM
whos given you this as a project ?
Whats your background experiance ?
11-06-2018 02:20 AM
This part of my project. And I am able to generate bitstream and able to flash. But issues in emulation, and that is where I am looking out for writing wrapper as per the details given above.
11-06-2018 02:21 AM
Are you aiming to run emulation ?
Whats your experience ?
what other designs have you done,