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steve77
Visitor
Visitor
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Registered: ‎06-28-2017

Need help with generating compatible FIFO with existing legacy test design

I dont have an XCI file and the core was generated likely with ISE (im not sure) but it uses version 13.2 of the Virtex 5 SIRF library... anyhow i need a compatible behavioral fifo for vivado 2020.2  - Granted i could probably eventually figure this out but any help would be greatly appreciated...   i just dont have time to debug this complicated test structure - it did work with the old SIRF libraries but they were lost.  Anyhow here is the structure im trying to recreate 

 

“fifo_generator_v4_4”   => "fifo_generator_v13_2”    - i only need this for sim so any target hardware will do - at the moment im using kintex ultrascale

again the question is ....how can i translate the below 4.4 fifo to equivalent 13.2 fifo - can anyone help.

 

<begin>

 

  for all : wrapped_special_block_v4_4 use entity XilinxCoreLib.fifo_generator_v4_4(behavioral)

    generic map(

      c_has_int_clk => 0,

      c_rd_freq => 1,

      c_wr_response_latency => 1,

      c_has_srst => 0,

      c_has_rd_data_count => 0,

      c_din_width => 36,

      c_has_wr_data_count => 0,

      c_full_flags_rst_val => 1,

      c_implementation_type => 2,

      c_family => "virtex5",

      c_use_embedded_reg => 0,

      c_has_wr_rst => 0,

      c_wr_freq => 1,

      c_use_dout_rst => 1,

      c_underflow_low => 0,

      c_has_meminit_file => 0,

      c_has_overflow => 1,

      c_preload_latency => 1,

      c_dout_width => 36,

      c_msgon_val => 1,

      c_rd_depth => 2048,

      c_default_value => "BlankString",

      c_mif_file_name => "BlankString",

      c_has_underflow => 1,

      c_has_rd_rst => 0,

      c_has_almost_full => 1,

      c_has_rst => 1,

      c_data_count_width => 11,

      c_has_wr_ack => 0,

      c_use_ecc => 0,

      c_wr_ack_low => 0,

      c_common_clock => 0,

      c_rd_pntr_width => 11,

      c_use_fwft_data_count => 0,

      c_has_almost_empty => 1,

      c_rd_data_count_width => 11,

      c_enable_rlocs => 0,

      c_wr_pntr_width => 11,

      c_overflow_low => 0,

      c_prog_empty_type => 3,

      c_optimization_mode => 0,

      c_wr_data_count_width => 11,

      c_preload_regs => 0,

      c_dout_rst_val => "0",

      c_has_data_count => 0,

      c_prog_full_thresh_negate_val => 2044,

      c_wr_depth => 2048,

      c_prog_empty_thresh_negate_val => 3,

      c_prog_empty_thresh_assert_val => 2,

      c_has_valid => 0,

      c_init_wr_pntr_val => 0,

      c_prog_full_thresh_assert_val => 2045,

      c_use_fifo16_flags => 0,

      c_has_backup => 0,

      c_valid_low => 0,

      c_prim_fifo_type => "2kx18",

      c_count_type => 0,

      c_prog_full_type => 3,

      c_memory_type => 1);

-- synthesis translate_on

BEGIN

-- synthesis translate_off

U0 : wrapped_special_block_v4_4

    port map (

      din => din,

      prog_empty_thresh => prog_empty_thresh,

      prog_full_thresh => prog_full_thresh,

      rd_clk => rd_clk,

      rd_en => rd_en,

      rst => rst,

      wr_clk => wr_clk,

      wr_en => wr_en,

      almost_empty => almost_empty,

      almost_full => almost_full,

      dout => dout,

      empty => empty,

      full => full,

      overflow => overflow,

      prog_empty => prog_empty,

      prog_full => prog_full,

      underflow => underflow);

-- synthesis translate_on

 

END special_block_v4_4_a;

 

<END>

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dpaul24
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214 Views
Registered: ‎08-07-2014

@steve77 ,

Are you aware of the FIFO parameters used with ISE? If yes, then use the same parameters to generate a FIFO using Vivado.

https://www.xilinx.com/support/documentation/ip_documentation/emb_fifo_gen/v1_0/pg327-emb-fifo-gen.pdf

Chapter 5 is for you.

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