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Annu_21
Newbie
Newbie
548 Views
Registered: ‎03-11-2021

Nested Loop in VHDL

Is nested For loop is synthesizable? Also, if we are using a nested for loop, what will be delay for each output. How the nested loop in vhdl is differing from C?

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

Any RTL, is very different to C.

For instance

    one very rarely uses variables, and loops are fairly uncommon,

 

It seems your starting,

   Strongly suggest that you stick to designing with signals,

     not least , they are visible in the simulator which you will spend most of your time in,

         do not go to synthesis till the simulation works,

Suggest you read this book

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

 

One thing to kepe in mind always whilst designing RTL

 

Remember your describing logic, 

    so think how you would do what you want to to in logic first, then describe it

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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u4223374
Advisor
Advisor
520 Views
Registered: ‎04-26-2015

A nested For loop can be synthesized exactly like any other For loop. The key thing to realise here is that in HDL, that means fully unrolling it. Putting a loop in your code is a way of making it easier to read/modify for a human, not a way of saving resources. As @drjohnsmith has said, loops are fairly uncommon - because they also make it very easy to generate huge amounts of hardware without realising it.

 

If you want to loop over a 640x480 image, for example, then using a For loop here (either a loop over 640 columns nested inside a loop over 480 rows, or a single loop over all 307200 pixels) will create 307200 copies of whatever is inside the loop. This will be a lot of hardware. Because it's all running in parallel, the delay for each output will be very nearly zero - it just depends on where the output is relative to where the hardware ends up being placed on the chip.

 

If you want a C-style loop (ie one processing unit that handles inputs one-at-a-time) then you need to understand how a finite state machine works, and implement that.

maps-mpls
Mentor
Mentor
108 Views
Registered: ‎06-20-2017

Just to add, for loops are not unheard of in VHDL. 

A for loop inside of a process is technically a "sequential loop" but when used in synthesizeable code it is usually describing concurrency (parallelism). 

For example, take a look at XIlinx's UG901, and the section with the source for bytewrite_tdp_ram_rf.vhd.  They have a for loop inside of a process, but it is simply generating code for each byte.  It could have, based on a quick look, also been coded up with a for...generate with a process on the inside of the for generate.  Or it could have been coded up manually as NB_COL different processes.  By using loops they are reducing the amount that has to be typed, and more importantly, maintained.  For an 8-byte memory, maintaining 8 different process has more opportunities for a typographical error, and more places to change if you want to switch from 8-byte to 8-shorts.

Point is, I use loops frequently in VHDL, but it is almost always to save typing, and as the others have mentioned, I understand what the tools will build as a result.  If you're still learning, open up a synthesized design and use the schematic view of the netlist.  It is quit useful if you're just starting out in VHDL.

And take a look at UG901, which has many examples of VHDL, some of which has for generates, other have for loop, and yet others for loops in functions.

*** Destination: Rapid design and development cycles ***
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