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Observer
Observer
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Registered: ‎04-19-2018

[Netlist 29-85] warning on PLL_ADV instance

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Hi all,

 

I am porting a design from Spartan6/ISE to Artix7/Vivado.

 

On some PLL instantiation, I get the following critical warning: [Netlist 29-85] One or more of the DRP ports of PLL_ADV instance 'U_CommonTopLevel/u_pll_adv' are connected to nets. The DRP ports are not supported for direct mapping to MMCM due to address changes, and must remain unconnected. DRP ports include DO, DRDY, DADDR, DCLK, DEN, DI, and DWE.

 

But in the instantiation all DRP ports are unconnected:

 

u_pll_adv
(
.CLKFBIN (clkfbout_clkfbin),
.CLKINSEL (1'b1),
.CLKIN1 (sys_clk_ibufg),
.CLKIN2 (1'b0),
.REL (1'b0),
.RST (1'b0),
.CLKFBOUT (clkfbout_clkfbin),
.CLKOUT0 (clk_adc)
);

 

 

Best regards.

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Moderator
Moderator
906 Views
Registered: ‎11-04-2010

Hi, @penlaebruno ,

I understand that you intend to keep the source code same for different devices, but it is only suitable for source code with no relationship with the device (General purpose code).

Since you are using the bottom level primitive(which is quite different for SP6/A7) in your source code,  these primitives are not suitable for portable purpose. 

In my opinion, Retargeting primitives with large difference is a high risk action.

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Moderator
Moderator
874 Views
Registered: ‎11-04-2010
HI, @penlaebruno ,
You can try to regenerate all MMCM/PLL IPs in the Artix7/Vivado Project and run the flow again.
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Highlighted
Observer
Observer
871 Views
Registered: ‎04-19-2018

Thanks, that was my backup plan.

 

This is not ideal for me since I want to keep the code working on both target and regenerating the MCMM will create a different instance depending on the target.

 

 

 

 

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Highlighted
Moderator
Moderator
907 Views
Registered: ‎11-04-2010

Hi, @penlaebruno ,

I understand that you intend to keep the source code same for different devices, but it is only suitable for source code with no relationship with the device (General purpose code).

Since you are using the bottom level primitive(which is quite different for SP6/A7) in your source code,  these primitives are not suitable for portable purpose. 

In my opinion, Retargeting primitives with large difference is a high risk action.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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Visitor
Visitor
148 Views
Registered: ‎08-06-2020

 

Hi Hong,

I'm new in Xilinx and Vivado.

How can you regenerate all MMCM/PLL IPs in the Artix7/Vivado Project and run the flow again?

 

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