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daryon
Adventurer
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Registered: ‎08-30-2018

Number of configuration bits used by design in Vivado

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Hi,

 

I am using Vivado 2017.3 targeting a Zedboard with a Zynq FPGA.

 

I have designed and implemented a design and generated bitstream that works properly. I am wondering whether it is possible to decode the number of configuration bits in FPGA that are used by the implemented design in the Vivado tool or any corresponding output file. Is it possible to extract this information?

 

Thanks in advance for your help and support.

 

Bests,

Daryon

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daryon
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Registered: ‎08-30-2018

Hi,

Thanks for your replies. I found the solution toward the number of configuration bitsusedin a design. I share it here for the other people who may have the same question.

 

In Vivado tool, inside the XDC file we can set the following constraint:

set_property essential.bits.seu yes [get_pots current_design]

By using this constraint, while the bitstream generation and .EBD file will also be generated. This file contains 0's and 1's. We write an script to count the number of 1's that will give us the number of bits used in design implementation.

 

Hope it can help.

Daryon

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12 Replies
ddn
Moderator
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Registered: ‎06-06-2018

Hi @daryon,

 

Vivado IDE can verify and/or readback the configuration data (i.e., .bit file) downloaded into an FPGA.

 

For more information please refer Chapter 7  of UG908 (v2018.2).

 

Regards,

Deepak D N

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lowearthorbit
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Registered: ‎09-17-2018

You can assume a bit in the bitstream that is a 1 is used, (rough first guess)

 

As the default for all bits is a 0.  The bits that would affect the result if flipped, are called critical bits and the only way to find them is to flip every bit, one at a time, and see which ones break things (there is no tool, nor means to find these ).  Bits that must change to create the bitstream are called essential bits.  They may not affect operation as they are masked in space (not used by the function) or time (not used at this clock edge).  The ratio of bits that matter to operation is called the Architectual Vulnerability Factor (AVF) or Design Vulnerability Factor (DVF).  So for most designs, it is from 2 to 10%.

 

Essential bits are ~ 10 to 35% of the bitstream;  Critical bits are ~ 2 to 10% of a bitstream (for a design > 80% of resources full).

 

Look at the SEM IP if interested in how to protect against bit flips or tampering.

daryon
Adventurer
Adventurer
2,182 Views
Registered: ‎08-30-2018

Hi,

Thanks for your replies. I found the solution toward the number of configuration bitsusedin a design. I share it here for the other people who may have the same question.

 

In Vivado tool, inside the XDC file we can set the following constraint:

set_property essential.bits.seu yes [get_pots current_design]

By using this constraint, while the bitstream generation and .EBD file will also be generated. This file contains 0's and 1's. We write an script to count the number of 1's that will give us the number of bits used in design implementation.

 

Hope it can help.

Daryon

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drjohnsmith
Teacher
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Registered: ‎07-09-2009

What are you expecting to get out of knowing the number of bits set to '1' ?

 

It tells you not a lot, 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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daryon
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Registered: ‎08-30-2018

@drjohnsmith, Good question. We will use the number of configuration bits set to 1 to calculate the cross-section of the implemented design that is a metric for robustness of the system.

drjohnsmith
Teacher
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2,156 Views
Registered: ‎07-09-2009
Robustness of the design ? Against bit flipping ?
Is this a standard metric ?

My thought is a '0' is just as valuable as a '1',
if either gets toggle the design may or may not be broken,
I'd have thought its the total number of bits , times by a factor to take account of the design , and how critical a bit flip would be .
i.e. a flip in a shift register might be critical if its used as a counter, but less critical if its used as a delay of video data say.
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lowearthorbit
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Registered: ‎09-17-2018

Well,

That will be an over estimate by a factor of 5 to 10, as the actual cross section of your design is likely between 2 and 10% of the bits, and almost never more than 10%.  Vivado reports the essential bits (still 2 to 4 x larger than the actual critical bits).

 

As an example, typical microblaze designs run 2%, while a crypto design might run 10%.

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lowearthorbit
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Registered: ‎09-17-2018

The default is 0,

So all unused interconnect, LUT are 0's.  0's might be essential, and a few critical, but in the grand scheme, statistics takes over.

As mentioned, report essential bits (TCL command) is really the best.  Also using the SEU FIT spreadsheet.

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daryon
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Registered: ‎08-30-2018

@lowearthorbit,

 

Thanks for your reply. Regarding your statement : " report essential bits (TCL command)". I do not know this command and how it works. Can you please elaborate more on it with an example using the correct and functional Tcl command?

Thanks,

lowearthorbit
Scholar
Scholar
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Registered: ‎09-17-2018

For that,

I leave you to read the documentation.  SEU mitigation, all the tools that Xilinx offers, all the features, too numerous to detail here.  Search in the search icon (top of this site).  

 

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lowearthorbit
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Registered: ‎09-17-2018

"set_property bitstream.seu.essentialbits yet [current_design]"

The build process now generated .edc file and give a statement in the log window saying 30% are essential bits.

 

(found by searching as directed in previous post)

daryon
Adventurer
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Registered: ‎08-30-2018

Thanks @lowearthorbit, this is exactly what I haveusedin my XDC file. I think it should be "yes" instead of "yet" which I know it is just a small typo.

 

"set_property bitstream.seu.essentialbits yes [current_design]"