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Scholar
Scholar
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Registered: ‎04-04-2014

ODELAY2 tap value not changing (VAR_LOAD)

Hi,

 

I am running on a Kintex7. I have (I admit) an unusual application of an ODELAY2 primitive I am currently testing. Behavioural simulation suggests the design should work but in practise it doesn't. I have monitored as many of the signals I can in hardware manager and they all seems to be correct, apart from the cntvalueout (current tap value) is fixed at zero.

 

Here is my design:

 

I am trying to continuously vary the delay on a clock output (to a device pin) pseudorandomly.  I created a 5 bit pseudorandom generator to connect to the cntvaluein port of the ODELAY2. 

 

My ODELAY2 parameters are:

generics

CINVCTRL = false

DELAYsrc=CLKIN

HIGH_PERFORMANCE_MODe = false

ODELAY_TYPE = VAR_LOAD

ODELAY_VALUE = 0

PIPE_SEL = FALSE

REFCLK_FREQUENCY = 200.0

SIGNAL_PATTERN = CLOCK

 

ports

cntvalueout  = tap value monitored directly by ILA core, clocked by same undelayed clock source as c, clkin below

dataout = delayed output clock, drives OBUFT

c = my undelayed clock source (70MHz ish)

cinvctrl = '0'

clkin = my undelayed clock source

cntvaluein = my 5 bit PRBS sequence

inc = '0'

LD = '1' (permanently...)

LDPIPEEN = '1'

ODATAIN = '0'

REGRST = connected to a reset that goes low a handful of cycles after configuration

 

So, in my ILA I can see:

- the cntvaluein changing correctly

- REGRST is zero

- the ILA core is running so the C, CLKIN inputs must be running 

- my cntvalueout is permanently zero

 

Looking at the documentation I can see no port dependencies no restrictions I am violating.

 

Am I okay to assert LD before REGRST is released? Any ideas as to what I have done wrong?

I can see fror the implemented design that the IDELAYCTRL is instantiated, in the same regionas the ODELAY2, and has a valid refclk input.

 

Thanks

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Scholar
Scholar
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Registered: ‎08-07-2014

Re: ODELAY2 tap value not changing (VAR_LOAD)

As I understand the docu, in VAR_LOAD mode the REGRST should be affecting anything. The REGRST affects the pipeline register.

 

LD = '1' (permanently...)

But from spec- When LD is pulsed the value present at CNTVALUEIN<4:0> will be the new tap value.

 

So I think you can try out and change LD so that it is pulsed (high when a new pseudo-random value needs to be loaded). Then observe CNTVALUEOUT. 

 

It is also necessary to inst the IDELAYCTRL primitive.

 

 

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Registered: ‎04-04-2014

Re: ODELAY2 tap value not changing (VAR_LOAD)


@dpaul24 wrote:

As I understand the docu, in VAR_LOAD mode the REGRST should be affecting anything. The REGRST affects the pipeline register.

 

LD = '1' (permanently...)

But from spec- When LD is pulsed the value present at CNTVALUEIN<4:0> will be the new tap value.

 

So I think you can try out and change LD so that it is pulsed (high when a new pseudo-random value needs to be loaded). Then observe CNTVALUEOUT. 

 

It is also necessary to inst the IDELAYCTRL primitive.

 

 


That was my main concern. I will try and pulse LD every other clock cycle then. This isn't ideal, I had hoped to change it every clock cycle, but this may be okay.

 

I will report back.

 

Thanks

 

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Registered: ‎04-04-2014

Re: ODELAY2 tap value not changing (VAR_LOAD)

Well pulsing the LD every other clock cycle did nothing to change it. The cntvalueout is still stuck at zero...

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Registered: ‎08-07-2014

Re: ODELAY2 tap value not changing (VAR_LOAD)

Well can't help you more on that. Maybe some Xilinx support personnel can.

 

But I can't agree more with your statement, "Behavioural simulation suggests the design should work but in practise it doesn't. "

I am currently struggling with a design having IDDR and the simulation results are completely different than what I observe on actual h/w with ILA cores inserted!

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Registered: ‎04-04-2014

Re: ODELAY2 tap value not changing (VAR_LOAD)


@dpaul24 wrote:

Well can't help you more on that. Maybe some Xilinx support personnel can.

 

But I can't agree more with your statement, "Behavioural simulation suggests the design should work but in practise it doesn't. "

I am currently struggling with a design having IDDR and the simulation results are completely different than what I observe on actual h/w with ILA cores inserted!


that's okay, thanks for helping

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Registered: ‎04-04-2014

Re: ODELAY2 tap value not changing (VAR_LOAD)

Hi,

 

I still cannot get my ODELAYs working and am running out of ideas.

 

I have reduced the complexity of my design as much as I can and added a VIO so that I can change certain parameters on the fly in hardware to see if I am doing something wrong.

 

I actually am trying to program 4 ODELAYS in the same bank. For sanity, I connected 1 as FIXED, with a delay tap of 5. My ILA monitor correctly shows CNTVALUEOUT for this ODELAY to be 5. Plus, I can see an output waveform on an oscilloscope when I measure on the board, so I know that the ODELAY there is working. The others have nothing on them.

 

The other 3 ODELAYs I cannot get to change from a tap value of 0. I have tried:

- Pulsing LD for 2 cycles, instead of 1

- Setting "PIPE_SEL" to False, incorrectly set this to True, even though I'm in VAR_LOAD mode

- Pulsing CE, instead of keeping it low, as the datasheet suggests. I'm not using INC/DEC

- Tying LDPIPEEN low, I has this tied high before.

- Keeping REGSRT low, as I'm not using pipeline mode. Before it was connected to my reset

 

As I say, I am trying to delay a clock signal, and this same (undelayed) clock signal clocks in the CNTVALUEIN with LD. This clock is running at 70MHz.

 

What am I doing wrong? Why are my VAR_LOAD ODELAYs stuck as zero and not outputting anything at all?

 

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Registered: ‎04-04-2014

Re: ODELAY2 tap value not changing (VAR_LOAD)

Okay, I maanged to get the CNTVALUEOUT to change, but I don't know why I needed to do the change I did.

 

I tried changing the delay input attribute from CLKIN to ODATAIN and the SIGNAL_PATTERN attribute from CLOCK to DATA. I tied the CLKIN input to '0' and the ODATAIN input to '1'. That is all I changed. Now I can see the CNTVALUEOUT changing as expected.

 

Can you not used VAR_LOAD with a CLKIN signal?

 

Come on guys, what's going on? I can find nothing in the documentation that says this behaviour is expected. I am re-reading as much as I can for anything I've missed and I can't see anything. Can someone explain?

 

Thanks

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