02-26-2015 08:30 AM
i have a really basic question regarding OSERDESE2. I am using it for 8:1 serialization in SDR mode and in the datasheet the examples show all the output starts with the rising edge of the slower clock (CLKDIV).
So, in my simulation the output is with D0 not after the rising edge. Now I have concerns about a correct instantiation or stimulation of this IP.
In the attachment you can see the offset.
Can you please tell me if this is "normal" for a 8:1 SDR or have I made a mistake and D0 should be aligned to CLKDIV?
Simulated with IES14
02-26-2015 10:51 AM
Is this simulation shot starting at time zero? If so it may be that global set/reset (GSR) is actually the gating factor in when the SERDES starts up rather than your falling edge on RST. Make sure that RST waits until a rising edge of CLKDIV after 100 ns.
03-03-2015 09:06 AM
I updated simulation and hold the reset of the OSERDES for more than 100ns active. It seems like before.
So is it correct to have such an offset?