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Participant
Participant
6,069 Views
Registered: ‎09-29-2011

OSERDES: clock to output data relationship

Hello,

i have a really basic question regarding OSERDESE2. I am using it for 8:1 serialization in SDR mode and in the datasheet the examples show all the output starts with the rising edge of the slower clock (CLKDIV).

 

So, in my simulation the output is with D0 not after the rising edge. Now I have concerns about a correct instantiation or stimulation of this IP.

 

In the attachment you can see the offset.

 

Can you please tell me if this is "normal" for a 8:1 SDR or have I made a mistake and D0 should be aligned to CLKDIV?

 

Vivado 2014.2

Simulated with IES14

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oserdese2.png
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Participant
Participant
6,065 Views
Registered: ‎09-29-2011

the picture is a bit small

 

here are some zooms for you..

 

Zoom1: Data to Clock

Zoom2: Reset

oserdes2_z1.png
oserdes2_z2_reset.png
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Professor
Professor
6,052 Views
Registered: ‎08-14-2007

Is this simulation shot starting at time zero?  If so it may be that global set/reset (GSR) is actually the gating factor in when the SERDES starts up rather than your falling edge on RST.  Make sure that RST waits until a rising edge of CLKDIV after 100 ns.

-- Gabor
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Participant
Participant
5,990 Views
Registered: ‎09-29-2011

Hello,

I updated simulation and hold the reset of the OSERDES for more than 100ns active. It seems like before.

 

So is it correct to have such an offset?

issue1.png
issue1_z1.png
issue1_z2.png
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