cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jameshua
Newbie
Newbie
431 Views
Registered: ‎08-20-2020

Openldi decoder

Hi,

I want to use SPARTAN to decode OpenLDI signal (one type of LVDS signal).

The sequence is like below.

One clock cycle contains 7 data.  

So does SERDES can handle it? Or i need to use PLL to generate 7x frequence clock? And how to align the data and clock?

Thanks. 

BTW, does xilinx have the IP core for this signal? 

jameshua_0-1597977219465.png

 

Tags (2)
0 Kudos
0 Replies