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asmundr
Visitor
Visitor
3,788 Views
Registered: ‎02-12-2014

[Opt 31-2] SRLC32E [...] is missing a connection on D pin.

Has anyone encountered this error message?

 

[Opt 31-2] SRLC32E i_mb_system/i_mb_system_bd/antifuse_nor_ctrl/U0/AXI_EMC_NATIVE_INTERFACE_I/RDATA_FIFO_I/DYNSHREG_F_I/INFERRED_GEN.data_reg[255][10]_srl32 is missing a connection on D pin.

 

It is completely embedded within a Block Design of mine, so I feel it is out of my control. I may be wrong. Grateful for any input!

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3 Replies
vemulad
Xilinx Employee
Xilinx Employee
3,780 Views
Registered: ‎09-20-2012

Hi,

 

Open synthesized design and track the D input of this SRL " i_mb_system/i_mb_system_bd/antifuse_nor_ctrl/U0/AXI_EMC_NATIVE_INTERFACE_I/RDATA_FIFO_I/DYNSHREG_F_I/INFERRED_GEN.data_reg[255][10]_srl32".

 

Check if it is connected properly in the design.

 

If it is not connected properly make changes to fix it. Else if you see it connected properly in synthesized design, try applying DONT_TOUCH attribute on the net connected to D pin of SRL and see if that preserves the logic driving SRL.

 

Open implemented design after this and see if the SRL input is connected properly.

 

Thanks,

Deepika.

Thanks,
Deepika.
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nicolas
Adventurer
Adventurer
1,093 Views
Registered: ‎04-26-2019

Hi @vemulad 

When you say "If it is not connected properly make changes to fix it" , what kind of change should it be ?

I have the issue with ILA ip. When i track the net in synthesized design i see this:

Annotation 2019-08-21 114954.jpg

 

 

 

 

 

 

 

 

 

 

 

I don't know how to fix that issue.

BR

 

 

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hossam1984
Participant
Participant
979 Views
Registered: ‎02-26-2019

Untitled.png

 

As shown above, you can know which Port/Pin is making this problem. The simple way is to remove the debug from this Port/Pin then try synthesize again. If you need to add it you can add it again.

I solved it by doing that.

 

Capture2.PNG

 

Good Luck

 

 

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