cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
richterfhg
Observer
Observer
258 Views
Registered: ‎04-14-2011

Overdrive LVDS with single ended for short time

Hello,

is it possible to "overdrive" a Artix 7 LVDS input (2.5V VCCO and internale termination) for a short time (some microseconds) with 1.8V single ended signals without damaging or degration?

Backgound: We want to use a LTC2259-14 ADC together with an Arxtix 7. As we have to transfer the parallel signal over a connector we want to use the LVDS mode of the ADC. The ADC is at power up in CMOS output mode and has to bring into LVDS mode by using the SPI registers. This takes some time and is done by the Artix. In this period of time, the voltage level on the inputs configured to LVDS is 1.8V single ended.

Is this possible or will the FPGA demaged or degraded? I took a look into the data sheet but it´s not fully clear to me what the maximum rating of 2.625 V is meaning.

Thanks a lot.

0 Kudos
2 Replies
229 Views
Registered: ‎01-22-2015

@richterfhg 

is it possible to "overdrive" a Artix 7 LVDS input (2.5V VCCO and internale termination) for a short time (some microseconds) with 1.8V single ended signals without damaging or degration?

Table 1 in datasheet, DS181(v1.25), for the Artix-7 describes conditions that could damage the Artix-7.  In your case, when VCCO=2.5V, a value for Vin of 1.8V is well below the absolute maximum value for Vin of (VCCO+0.55 = 3.05V).  So, the 1.8V single-end signal should not damage your LVDS_25 inputs on the Artix-7.

However, I am concerned that your 1.8V signal may damage the 100-ohm internal termination (DIFF_TERM) of the Artix-7. 

From Table 11 of DS181, we find that VIDIFF(max)=0.600V.  A voltage of 0.600V across 100-ohms means that DIFF_TERM can dissipate (0.600^2/100 = 3.6mW) of heat.  However, 1.8V across 100-ohms is (1.8^2/100 = 32.4mW) of heat, which I'm not sure that DIFF_TERM can handle.

So, unless you get guidance from Xilinx on this, plan to use an external 100-ohm termination (that can handle 32.4mW) for your LVDS input to the Artix-7 (and plan not to use DIFF_TERM).  

Cheers,
Mark

0 Kudos
richterfhg
Observer
Observer
198 Views
Registered: ‎04-14-2011

Thanks for now. I´m also concerned about the DIFF_TERM. I cannot find any information about the maximum power dissipation. As the "base board" including the FPGA is ready made and also used in other projects, we cannot use external terminimation. We try to find out if it´s possible to let the VCCIO of the ADC to zero until it´s configured by SPI. Maybe a Xilinx expert has a hint regaring the DIFF_TERM max power dissipation.

0 Kudos