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Visitor daniel_leu
Visitor
7,351 Views
Registered: ‎08-05-2015

PCIe I/O assignment does not match datasheet

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I am using a xc7a100tfgg484 with a 4 lane PCIe interface (AXI memory mapped to PCIe core) with Vivado 2015.4.

 

This is the PCIe pin assignment out of Vivado:

PCIe pins

 

But this is the reversed order from what the datasheet says:

 

Pin   Pin Name                      Memory Byte Group  Bank  VCCAUX Group  Super Logic Region  I/O Type  No-Connect
A8    MGTPRXN0_216                  NA                 216   NA            NA                  GTP       NA
C9    MGTPRXN3_216                  NA                 216   NA            NA                  GTP       NA
A10   MGTPRXN2_216                  NA                 216   NA            NA                  GTP       NA
C11   MGTPRXN1_216                  NA                 216   NA            NA                  GTP       NA
Source: http://www.xilinx.com/support/packagefiles/a7packages/xc7a100tfgg484pkg.txt

 

 

I can reproduce this with the sample design extended to 4 PCIe lanes. Why does the PCIe pinout not match what the datasheet specifies? 

 

Thanks!

 

- Daniel

 

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Xilinx Employee
Xilinx Employee
13,188 Views
Registered: ‎08-13-2007

Re: PCIe I/O assignment does not match datasheet

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They are two different things... One is the PCIe lane assignment - the other is [one of] the GTP coordinate systems

 

See PG054 (page 259 currently, v3.2) for the PCIe to transceiver XY coordinates

then see UG482 (page 247, v1.8) for the GTP mappings between XY, package ball, and index/tile number schemes...

 

It can be confusing until you understand these numbering schemes.

 

Cheers,

bt

2 Replies
Xilinx Employee
Xilinx Employee
13,189 Views
Registered: ‎08-13-2007

Re: PCIe I/O assignment does not match datasheet

Jump to solution

They are two different things... One is the PCIe lane assignment - the other is [one of] the GTP coordinate systems

 

See PG054 (page 259 currently, v3.2) for the PCIe to transceiver XY coordinates

then see UG482 (page 247, v1.8) for the GTP mappings between XY, package ball, and index/tile number schemes...

 

It can be confusing until you understand these numbering schemes.

 

Cheers,

bt

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Visitor daniel_leu
Visitor
7,343 Views
Registered: ‎08-05-2015

Re: PCIe I/O assignment does not match datasheet

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Hi BT,

 

Thank you for the quick reply and the explanation! 

 

So Lane 0 is on X0Y7 which uses MGTPRXN3_216. This means that 0..3 in MGTPRXN[0..3] do not match lanes 0..3. I guess there is a good reason for that ;-)  

 

Thanks,

Daniel

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