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mwerner2000
Adventurer
Adventurer
4,572 Views
Registered: ‎06-05-2015

PCIe and Additional USer Logic with GTPs in one Quad

Dear Ladies and Gentlemen,

 

can I use the remaining GTPs for another application, when using a PCIe x1 port in the same GTP Quad? My application requires a x1 PCIe link and two GTPs for a custom application. The line rates of PCIe would be 5 Gbps and the custom GTPs need a line rate of 2.5 Gbps. The reference clock could be shared between them. I am worrying about the statements mentioned in PG054 v3.3 on page 176 ("Tandem PROM/PCIe Resource Restrictions"), which state that the entire Quad is lost for user application, when using PCIe. Does this only relate to the tandem configuration or is this a general issue, because the GTP common may not be used for another application, when using PCIe?

 

Thank you very much in advance.

 

Sincerely,

Martin Werner

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2 Replies
saradapr
Explorer
Explorer
4,545 Views
Registered: ‎10-14-2015

Hi @mwerner2000,

 

Please refer to the similar discussion:

 

https://forums.xilinx.com/t5/PCI-Express/Tandem-PROM-on-Zynq-DRC-place-errors/td-p/694203

https://forums.xilinx.com/t5/PCI-Express/Does-the-Tandem-constraints-include-slices-and-routing-resource/td-p/678115

 

Thanks,

Sarada

 

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mwerner2000
Adventurer
Adventurer
4,522 Views
Registered: ‎06-05-2015

Dear Sarada,

 

Thank you for your answer. I am not planning to use the Tandem configuration, because it is not available for Artix-7 FPGAs. I am just wondering if there is a technical reason, why the PCIe core should consume the other 3 GTPs in the same quad. Let's just assume I am not using tandem nor partial reconfiguration and the line rates of the PCIe and the other 2 GTPs will be the same. Can I use the other 3 GTPs for anything else than PCIe?

 

Sincerely,

Martin Werner

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