08-30-2018 01:03 PM
I'm using Vivado 2018.1, PCIe Endpoint v3.3, [system] verilog.
So how could the absence of the "application" cause the SBC to not finish booting? Are there transactions handled at the "application" level, which is above the PCIe Endpoint v3.3 level, where the absence of this handling causes such a hang?
I know you're going to ask why I want to remove the application. The fact is that this then replicates my results for a 4-lane Xillybus demo that causes the same SBC boot hang. The Xillybus demo has a "xillybus_core.v" at the same logical position as the "application" (pcie_app_7x). In asking how the PCIe Endpoint demo might hang the boot, I'm really trying to figure out if and how the xillybus_core.c might be hanging the SBC boot. Otherwise, I've confirmed all of my players here by different means or on different FPGA platforms. Xillybus works. PCIe Endpoint demo works. Everything works in one way or the other, outside of the scenario I actually need.
Thanks VERY much,