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Registered: ‎08-07-2020

PLL DRC PDRC-43 issue

Hello,

I tried to generate a clock with a PLL.

The input clock is a 119MHz and the outputs are 59.5 MHz and 416,5 MHz.

Via the Clock wizard i generate a PllE2_adv with the following parameters:

BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => 7,
CLKFBOUT_PHASE => 0.000000,
CLKIN1_PERIOD => 8.403000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT1_DIVIDE => 14,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 4,
IS_CLKINSEL_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
STARTUP_WAIT => "FALSE"

 

And then during implementation i got the following issue:

[DRC PDRC-43] PLL_adv_ClkFrequency_div_no_dclk: The computed value 455.000 MHz (CLKIN1_PERIOD, net Video_Clock) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X1Y0
(cell i_LvdsTransmitter/i_LvdsTxClockGenerator/plle2_adv_inst) falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1866.000 MHz).
The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (15.384615),
multiplication factor CLKFBOUT_MULT_F (7) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

Did you have an idea on how to solve this issue?

 

Best Regards,

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Moderator
Moderator
518 Views
Registered: ‎08-08-2017

Hi @RomainDelcroix 

This is bit unexpected using clocking wizard as M, D , and O values are getting set appropriately in clocking wizard.

Can you please share the clocking wizard .xci file , device part and VIVADO version used for this project.

As a workaround , check the cell properties of PLL and look for the values M (CLKFBOUT_MULT ) and  D (DIVCLK_DIVIDE)

VCO freq =  (input frequency * M)/O ,

Adjust the either M or O to have VCO frequency between (800.000 - 1866.000 MHz).

Running VCO at maximum frequency is recommended.

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Registered: ‎08-07-2020

What did you mean by

This is bit unexpected using clocking wizard as M, D , and O values are getting set appropriately in clocking wizard.

I'm using vivado 2020.1

I don't reach to attached the xci files

The attachment's clk_wiz_0.xci content type (application/octet-stream) does not match its file extension and has been removed.

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Moderator
Moderator
498 Views
Registered: ‎08-08-2017

Hi @RomainDelcroix 

As per Input frequency and set output frequencies , clocking wizard will calculate the M , D and 0 values .

Fvco =  (Fin * M)/D

and Fout  = Fvco/0

Anyways can you please post here the screenshots for all tabs in the clocking wizard , Based on that i will check this at my end.

As suspect earlier , the set parameters in clocking wizard are not propogated properly in Implementation phase .

 

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Moderator
Moderator
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Registered: ‎08-08-2017

Hi @RomainDelcroix 

yes .xci attachement is not supported , you can create a zip and attach.

 

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489 Views
Registered: ‎08-07-2020

In fact i just used the wizard to define the parameters and then i instanciate the following blocks:

i_Pll : PLLE2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => 7,
CLKFBOUT_PHASE => 0.0,
CLKIN1_PERIOD => 8.403,
CLKIN2_PERIOD => 8.403,
CLKOUT0_DIVIDE => 2,
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT0_PHASE => 0.0,
CLKOUT1_DIVIDE => 14,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0,
CLKOUT2_DIVIDE => 7,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT2_PHASE => 0.0,
CLKOUT3_DIVIDE => 7,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT3_PHASE => 0.0,
CLKOUT4_DIVIDE => 7,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT4_PHASE => 0.0,
CLKOUT5_DIVIDE => 7,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
REF_JITTER1 => 0.100
)
port map(
CLKFBOUT => Feedback,
CLKOUT0 => TxClock_i,
CLKOUT1 => DualClock_i,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
PWRDWN => '0',
LOCKED => Locked,
CLKFBIN => Feedback_i,
CLKIN1 => ClockIn,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => x"0000",
DWE => '0',
RST => Reset
);

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Moderator
Moderator
467 Views
Registered: ‎08-08-2017

Hi @RomainDelcroix 

This is not matching with instantiation you shared earlier where DIVCLK_DIVIDE = 4.

In current instantiation , DIVCLK_DIVIDE = 1 , 

 CLKIN1_PERIOD => 8.403  i.e input frequency Fin = 119 MHz

CLKFBOUT_MULT (M) = 7.

So the VCO frequency =  (119*7)/1 = 833 which is withing the limit

  CLKOUT0 = 833/2 = 416.5 

  CLKOUT1 = 833/14 = 59.5

This instantiation should work .

 

 

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Registered: ‎08-07-2020

Ok, but i have the following message

[DRC PDRC-43] PLL_adv_ClkFrequency_div_no_dclk: The computed value 455.000 MHz (CLKIN1_PERIOD, net Video_Clock) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X1Y0 (cell i_LvdsTransmitter/i_LvdsTxClockGenerator/i_Pll) falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1866.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (15.384615), multiplication factor CLKFBOUT_MULT_F (7) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

 

I don't understand why the CLKINx_PERIOD is 15.384615?

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Moderator
Moderator
432 Views
Registered: ‎08-08-2017

Hi @RomainDelcroix 

Yes this unexpected .

Can you please open the implemented design , -> Check the PLL in the netlist -> Check the cell properties.

I believe the CLKINx_PERIOD  is wrongly propagated, you can edit the  "CLKINx_PERIOD" attribute in cell properties to actual CLKIN_PERIOD 

and re run the implementation.

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Registered: ‎08-07-2020

How i can do that the implementation section is not accessible? And I don't find the Check the cell properties.

 

RomainDelcroix_0-1596800983360.png

On this design i have an other PLL, who provide the 119MHz. It's an issue?

 

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Registered: ‎08-07-2020

It's not solving the issue

RomainDelcroix_0-1596802104940.png

 

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Moderator
Moderator
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Registered: ‎08-08-2017

Hi @RomainDelcroix 

#1 Open the Schematic after implementation , 

#2 Search for the PLL in discussion , 

#3 Check the cell properties for that PLL  (i.e CLKIN_PERIOD, M , D value)

You will observe that it is not matching with parameters set by wizard.

#4 edit the incorrect CLKIN_PERIOD property with correct CLKIN period  and re-run the implementation.

 

 

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Reply if you have any queries, give kudos and accept as solution
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Highlighted
137 Views
Registered: ‎08-07-2020

Ok, I remove one of the two PLLs and it solve my issues. Changing the settings was not solving the problem.

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Newbie
Newbie
51 Views
Registered: ‎09-08-2020

Hi Newbie,

I'm facing the same issue. Plz explain me step by step how you proceed to solve this issue.

Thank you

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