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Visitor
Visitor
10,333 Views
Registered: ‎11-21-2012

PLL/MMCME DRP - C code

Hi All.

 

1) I would like to reconfig CMTs through DRP port, by using C code running on Microblaze.

 

2) There is XAPP888 which describes the DRP access procedure and has a reference design which is based on state machine, and which contains a verilog header file with all the calculation/lookup functions, of course written in verilog.

 

3) The Microblaze in my design is connected to the DRP port of the CMT through AXI4-to-DRP bridge (custom code which is verified to work correctly), there is something similar in XAPP1214, but there is no code in C).

 

4) My problem is now translating verilog to C (which is problematic as I am not proficient in both of them), and I would like to know if there is already code in C for that, perhaps in some peripheral's driver.

 

5) The device in question is Kintex-7, 325T on a custom board. The environment is Planahead 14.3.

 

Thanks in advance.

 

Igor K.

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Visitor
Visitor
10,330 Views
Registered: ‎11-21-2012

Sorry, forgot to mention:

 

I've implemented XAPP888 previously with PLLE2, but only as a state machine which was configuring a setting out of a table of around 10 settings. Now I need to reconfigure some arbitrary frequency and not a preset one.

 

Sorry again.

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Adventurer
Adventurer
9,804 Views
Registered: ‎04-27-2011

I'll second this request.  Now that Xilinx has released an AXI<->DRP bridge it would profoundly useful if some sample C code were made available to demonstrate reconfiguring an MMCM using parameters much like those used for input to the MMCM configuration Wizard.  I'm using a Kintex-7.

 

I've googled like crazy, but I simply can't find straightforward documentation that tells me how to perform DRP reconfiguration of an MMCM (short of running a Verilog sim from Jim Tatsukawa's app note).

 

Thanks,

 

Stacey

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Contributor
Contributor
9,678 Views
Registered: ‎04-23-2008

...and it would help if there were proper DRP timing details instead of "see XAPP888 code"  - I dare say I could decode the verilog into vhdl given time and avoiding the project manager's "hows it going?" - answer  "I'm just learning Verilog for the next couple of days!" 

If someone knows where proper documentation resides could they let us know.  Many thanks!

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Adventurer
Adventurer
9,666 Views
Registered: ‎04-27-2011

I've finally got MMCM DRP working from my Microblaze (Kintex-7) for my extremely simple requirements (two MMCM configurations with 3 outputs, with all outputs phase locked, and a different CLKIN1 frequency for each configuration).  Here's what I did:

 

  1. Added the AXI4-Lite DRP Bridge to my system.
  2. Ran the MMCM Wizard for configuration 1.
  3. Wrote some C code to dump the MMCM DRP registers to a COM port.
  4. Synthesized/built my project and loaded and ran it on my hardware.
  5. Dumped the DRP regs.
  6. Repeated 2-5 for the 2nd MMCM configuration.
  7. Stored both configurations as static unsigned short arrays in C and wrote some code to load either, then reset the MMCM.
  8. Probed the 3 clocks, they all appear to be running at the correct frequencies for each DRP config.

Gotchas:

  • My CLKIN1 frequency is different between my config 1 and 2.  CLKFBOUT_MULT_F is not DRP-able.  Make sure that you use the same CLKFBOUT_MULT_F for all the MMCM Wizard runs, because whatever you instantiate for the MMCM is what all DRP configurations will need to use.
  • DIVCLK_DIVIDE is DRP-able, so use this against the "best" constant CLKFBOUT_MULT_F to keep the VCO frequencies in range.  The MMCM Wizard will let you know if you get the VCO frequency out of range.
  • The MMCM DRP regs are not contiguous in DRP address space.  See Table 15 of the xapp888 application note.
  • The PowerReg bits apparently need to be all set when performing DRP according to the app note.
  • If the instantiated MMCM has clock outputs that are slower than one of the DRP reconfigurations, then make sure those clocks are correctly constrained in the XDC file to match their fastest DRP frequencies.
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Advisor
Advisor
9,658 Views
Registered: ‎12-03-2007

Hi,

 

Any ideas on how to connect AXI4-stream to DRP using existing components ?

I didn't find any bridge between AXI4-Lite to DRP.

 

Thanks,

Evgeni

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Adventurer
Adventurer
9,572 Views
Registered: ‎04-27-2011

The AXILite-DRP bridge doesn't appear in the stock Vivado IP catalog (at least for 2014.4), it has been released as sample IP with an application note:

 

http://www.xilinx.com/support/documentation/application_notes/xapp1214-drp-bridge.pdf

 

I had to copy the IP into a local directory and add a user IP path to my project.

 

Stacey

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Observer
Observer
8,955 Views
Registered: ‎09-30-2009

There is an IP that supports this and includes the SW driver:

https://www.logicbricks.com/Products/logiCLK.aspx

 

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Xilinx Employee
Xilinx Employee
8,951 Views
Registered: ‎04-16-2012

Hi,

 

Check the section "Dynamic Reconfiguration through AXI4-Lite" in the following guide: http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf

 

Thanks,

Vinay

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