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arevhamb
Visitor
Visitor
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Registered: ‎10-10-2017

PLL clock generation

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Hi All,

 

I'm trying to generate clock of frequencies 143MHz and 167MHz using user clock as an input for PLL. The input user clock frequency is 156.25MHz.

 

The PLL lock signal is showing that the PLL is locked, but when checking the clock signal on the FMC connector, I can see the frequency is not constant.

 

Does anybody know what can be the reason? I was able to successfully generate 100MHz, 133MHz and 200MHz clocks, but in case of 143MHz and 167MHz clocks, the clock frequency is not stable, while PLL is shown as locked.

 

Thanks,

Arevik

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arevhamb
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Visitor
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Registered: ‎10-10-2017

Hi Ashishd,

 

Thank you for your quick response. I have figured out it was issue of the logic analyzer, with which I was checking the clock. I have rechecked the clock generated with Oscilloscope, and it appears the frequency was correct. 

 

Thank you for your help.

 

Arevik

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arevhamb
Visitor
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2,631 Views
Registered: ‎10-10-2017

Forget to note that I'm using KC705 evaluation board.

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ashishd
Xilinx Employee
Xilinx Employee
2,627 Views
Registered: ‎02-14-2014

Hi @arevhamb,

 

How much variation do you observe in output clock while generating 143 MHz and 167 MHz clocks?

I suspect the problem to occur because when I am selecting these numbers for input and output clocks in clocking wizard. I am not getting Actual frequencies to be same as those of Requested ones.

Please check this snapshot.

 

clocks.PNG

 

Is this same variation which you want to notify?

Regards,
Ashish
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ashishd
Xilinx Employee
Xilinx Employee
2,555 Views
Registered: ‎02-14-2014

Hi @arevhamb,

 

Did it help to figure out root cause of issue?

Regards,
Ashish
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arevhamb
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Visitor
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Registered: ‎10-10-2017

Hi Ashishd,

 

Thank you for your quick response. I have figured out it was issue of the logic analyzer, with which I was checking the clock. I have rechecked the clock generated with Oscilloscope, and it appears the frequency was correct. 

 

Thank you for your help.

 

Arevik

View solution in original post

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ashishd
Xilinx Employee
Xilinx Employee
2,545 Views
Registered: ‎02-14-2014

Hi @arevhamb,

 

Good to know.

Close the thread in the interest of others by marking a post as solution.

Regards,
Ashish
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