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Visitor
Visitor
796 Views
Registered: ‎09-09-2017

Path delay reduction

I am using spartan 6 series FPGA (XC6SLX150T) for connecting two points as a bridge without any logic other than connection.

What are possible ways to reduce the path delay using attributes, path constraints or any other?

Tool : ISE 14.7

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13 Replies
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Teacher
Teacher
775 Views
Registered: ‎07-09-2009

Re: Path delay reduction

What is your experience ?
What is your design language ?
what is your local support like ?

Delays in an FPGA are defined in the constraints file,
probably in your case , your using ISE, its a UCF file.

timing are measured between clocked resources ( registers ) , and also between registers and the IO pins.

Its the job of the tools to lay out your design to meet your timing requirements, If they cant. they fail,


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Visitor
Visitor
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Registered: ‎09-09-2017

Re: Path delay reduction

Mine is an assign statement in verilog to connect one input in one bank to the output in other bank. I want to reduce the routing delay. There are no clocking elements. Every thing is purely a combinatorial even that too assign statements.

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Mentor
Mentor
698 Views
Registered: ‎06-16-2013

Re: Path delay reduction

Hi @m.rajesh 

 

Can you accept to add pipeline ?

If yes, add flip flops between wns point.

 

Best regards,

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Visitor
Visitor
683 Views
Registered: ‎09-09-2017

Re: Path delay reduction

Pipelinening is fine when there's a clock in the design. Mine is completely combinatorial. Can anyone let me know ways to reduce 'net type' delay.

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Mentor
Mentor
673 Views
Registered: ‎06-16-2013

Re: Path delay reduction

Hi @m.rajesh 

 

Would you consider the following option ?

 

- Register duplication

- Register balancing

- Move 1st flip flop stage

- Move last flip flop stage

- Pack I/O registers into IOBs

- Reduce control sets

- Optimize instantiated primitives

 

Best regards,

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Adventurer
Adventurer
657 Views
Registered: ‎07-16-2009

Re: Path delay reduction

Hi @m.rajesh ,

I believe, you are looking for "set_input_delay" and "set_output_delay" commands.

 

Jan

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Teacher
Teacher
656 Views
Registered: ‎07-09-2009

Re: Path delay reduction

how to design without a clock ?
Thats a good question,

99.9 % of all designs I see I'd say were synchronous so, apologies we tend to think that way,

Can I check, Are you talking the asynchronous delay, pin to pin ?
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Teacher
Teacher
654 Views
Registered: ‎07-09-2009

Re: Path delay reduction

I seem to remember set_input_delay" and "set_output_delay are measured off clocks, this user says they have no clock ?
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Adventurer
Adventurer
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Registered: ‎07-16-2009

Re: Path delay reduction

Hi @drjohnsmith ,

I am on very think ice here, since most of my experience on these issues comes from different FPGA vendor, but when working on these different FPGAs we used concepts of virtual clocks.

You simply defined clocks that were not existing in the design and the used these clocks to reference the constraints. I believe, that something similar could be done here. You would define clocks with some period and set min and max delays in reference to these clocks. No register between input and output only means that you would have to be able to travel whole path in one period. But i freely admit I may be completely wrong.

 

Jan

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Teacher
Teacher
618 Views
Registered: ‎07-09-2009

Re: Path delay reduction

I think what you want to do is described here on page 99
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug903-vivado-using-constraints.pdf

As I said above, I don't think I have ever had to set pin to pin delay , so please try .

the commands you want for the XDC are
set_max_delay <delay> -from {node list} -to {node list}
set_min_delay <delay> -from {node list} -to {node list}
where the nodes are the input and output pins,
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Mentor
Mentor
590 Views
Registered: ‎06-16-2013

Re: Path delay reduction

Hi @m.rajesh 

 

Unfortunately, because you use ISE, you can't use "set_max_delay" and "set_min_delay" command.

So, would you refer my previous suggestion ?

 

Best regards,

Highlighted
Adventurer
Adventurer
546 Views
Registered: ‎04-04-2018

Re: Path delay reduction

You should be able to add a TNM to your IO constraints in .UCF file

NET "INPUT_0" TNM= "input_pads";
NET "INPUT_1" TNM= "input_pads";

NET "OUTPUT_0" TNM= "output_pads";
NET "OUTPUT_1" TNM= "output_pads";

and then constraint them this way.

TIMESPEC “TSintoout” = FROM “input_pads ” TO “output_pads” 10 ns;

Refer to UG625:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf
Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com
Highlighted
Guide
Guide
515 Views
Registered: ‎01-23-2009

Re: Path delay reduction

@markgraf gave the proper commands to constrain a combinatorial path through the FPGA in ISE. However, it is unlikely to make much of a difference; if the FPGA is empty (or near empty) then this route is probably already close to as fast as it can be. But you should still add the constraints.

You have to understand what you are asking the device to do:

  • Bring in a signal from the board. This must go through an input buffer (IBUF), which converts the board level I/O standard to an internal signal
  • Route the internal signal from the IBUF to an output buffer (OBUF) through general fabric routing
    • The fabric routing goes "hop to hop" through switch matricies over relatively short fabric routes (a couple of CLBs), so depending on how physically far the input pin is from the output pin (on the FPGA die), then it may have to go through many hops. Each of these costs time
  • Drive the signal through an output buffer (OBUF). This convers the internal signal to a board level I/O standard. Depending on the I/O standard, the drive strength and the slew rate of the OBUF (all of which are programmable), the can be VERY slow - upwards of 8ns for the bufer alone
    • You can look at changing the DRIVE and SLEW parameters of the OBUF to make them faster, but even at the fastest, this is still going to take a couple of nanoseconds

So, in the end you need to realize that FPGAs aren't optimized for combinatorial paths through the FPGA - these paths are not expected to be particularly fast...

Avrum