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Visitor kalkura
Visitor
381 Views
Registered: ‎08-29-2018

Period constraints for PLL/mmcm generated clock - 7 series FPGA devices

Are there timing arc between PLL/MMCM generated/output clocks and input to the same PLL? Is it necessary to give create_generated_clock constraint for those clocks or are we supposed to  write create_clock constraint?

 

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Xilinx Employee
Xilinx Employee
363 Views
Registered: ‎06-06-2018

Re: Period constraints for PLL/mmcm generated clock - 7 series FPGA devices

Hi @kalkura,

 

Most generated clocks are automatically derived by the Vivado Design Suite timing engine which recognizes the Clock Modifying Blocks (CMB). 

MMCM and PLL are CMB's. Refer UG906 for more information.

 

MMCM/PLL outputs are auto derived clocks, there no need to define create_generated clock constraint. Constraint is not required for that timing arc.

 

You can verify that auto generated clock at input pin of PLL by command get_clocks -of_objects [get_pins ].

 

Regards,
Deepak D N

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