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Registered: ‎06-04-2019

Phase shift of output clock of a pll

I am using a spartan 6 board. I want to change the phase of the output clock by sending some input signal to the PLL. What I think is I need to use "Dynamic phase shift ports", but I don't know how to use them. So, what signals I need to send for the phase of the output clock to be changed?

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Registered: ‎05-02-2017

 

hi @prasad_121601032 

 

Please see the below application note:

 

https://www.xilinx.com/support/documentation/application_notes/xapp879.pdf

This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Spartan®-6 FPGA Phase Locked Loop (PLL) through its Dynamic Reconfiguration Port (DRP). An explanation of the behavior of the internal DRP control registers is accompanied by a reference design. The reference design uses a state
machine to drive the DRP to ensure that the registers are controlled in the correct sequence.


Caution! If post-configuration cyclic redundancy check (CRC) functionality is needed in the design,the PLL DRP port cannot be used to dynamically reconfigure the PLL. Use of the PLL DRP port breaks the functionality of post-configuration CRC. Although the reference design performs the operations for the user, familiarity with the functional operation of the PLL is recommended. The PLL used in conjunction with the DRP interface is recommended for advanced users when the basic PLL functionality is not sufficient.


The DCM_CLKGEN primitive can be a useful alternative to using the PLL with the DRP interface. For more information on PLL functionality, see UG382, Spartan-6 FPGA Clocking Resources User Guide.

 

https://www.xilinx.com/support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf

This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock manager (MMCM) for the Xilinx 7 series, UltraScale, and UltraScale+ FPGAs. Similarly, the phase-locked loop (PLL) can be changed through the dynamic reconfiguration port (DRP). An explanation of the behavior of the internal DRP control registers is accompanied by a reference design that uses a state machine to drive the DRP, which ensures the registers are controlled in the correct sequence.

 

let me know your inputs

 

 

Regards
Chandra sekhar
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