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Visitor
Visitor
15,393 Views
Registered: ‎01-09-2013

Place 30-99 Errors in Place Design

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hello, this is cho.

 

when I using vivado, I encounted in error.

 

Place 30-99 Placer failed with error: 'Could not place BUFG'

Please revies all ERROR, CRITCAL WARNING and Warning messages...

 

But Projcet Summary showed Utilization,

And it said, BUFG Utilization is only 41%.

 

Why this error is occured??

Please give me your help.. 

Thanks.

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Participant
Participant
20,652 Views
Registered: ‎07-03-2013

There are multiple reasons why the placer can fail to place the BUFGs even when you are not utilizing all of them:


Here's some example reasons that may give you some info:

  1. If the BUFG and associatd I/O pin or other clock source (e.g. MMCM/PLL/DCM/SERDES) is not located in the correct location to allow a dedicated clock backbone route to the BUFG the placer can fail.  Usually you can overide this rule and allow non-dedicated routing to the BUFG if you can tollerate the increased insertion delay.
  2. Although there are Lots of BUFGs in most devices, you cant use all of them simulataneously without floorplanning your design to limit the number of different clocks per region.  The rules vary by device family so look in your targets clocking resource guide (e.g. per UG362 Page 13, Virtex-6 has 32 BUFGs but only 12 different clocks per region are allowed).  
  3. There are other placement rules for optimal connections between BUFGs and SERDES/MMCMs that require them to be in the same upper/lower half of the SLR if your using a V7 device as well.

With clock networks, it's always best to assign fixed locations to the dedicated components to make sure your results are repeatable and to understand the topology as it affects QOR, or in your case the ability to place & route at all.

 

Regards,

Digital Design Golden Rule: If its not tested - its broken.

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Professor
Professor
15,390 Views
Registered: ‎08-14-2007

Most FPGA's have more BUFG's than can actually be used at one time unless you are very

careful about restricting the number of clocks required in any one clock region.  There are also

restrictions for routing signals into a BUFG from device pins.  Sometimes using too many

clock capable pins to drive BUFG's can create an unroutable design.  The error message

suggested that you review the critical warnings.  Perhaps there is more information in the

warnings that can help you solve the problem.

-- Gabor
Visitor
Visitor
15,383 Views
Registered: ‎01-09-2013

Thanks for your reply Gabor.

 

But actually there is no critical warning...

So, I can't find the reason easily :(

 

 

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Participant
Participant
20,653 Views
Registered: ‎07-03-2013

There are multiple reasons why the placer can fail to place the BUFGs even when you are not utilizing all of them:


Here's some example reasons that may give you some info:

  1. If the BUFG and associatd I/O pin or other clock source (e.g. MMCM/PLL/DCM/SERDES) is not located in the correct location to allow a dedicated clock backbone route to the BUFG the placer can fail.  Usually you can overide this rule and allow non-dedicated routing to the BUFG if you can tollerate the increased insertion delay.
  2. Although there are Lots of BUFGs in most devices, you cant use all of them simulataneously without floorplanning your design to limit the number of different clocks per region.  The rules vary by device family so look in your targets clocking resource guide (e.g. per UG362 Page 13, Virtex-6 has 32 BUFGs but only 12 different clocks per region are allowed).  
  3. There are other placement rules for optimal connections between BUFGs and SERDES/MMCMs that require them to be in the same upper/lower half of the SLR if your using a V7 device as well.

With clock networks, it's always best to assign fixed locations to the dedicated components to make sure your results are repeatable and to understand the topology as it affects QOR, or in your case the ability to place & route at all.

 

Regards,

Digital Design Golden Rule: If its not tested - its broken.

View solution in original post

Participant
Participant
15,345 Views
Registered: ‎07-03-2013

Sorry since this is the V7 forum; you should look at UG472; but the same rules apply: no more than 12 BUFGs per region.

 

For V7 & SLR devices, here's some more examples of the placement rules you have to follow:

# <<<<<< Clock Rule: rule_mmcm_bufg >>>>>
# <<<<<< Clock Rule: rule_pll_bufg >>>>>
# Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
# Rule Description: A PLL driving a BUFG must be placed on the same half side (top/bottom) of the device

# <<<<<< Clock Rule: rule_mmcm_mmcm >>>>>
# Rule Description: An MMCM driving an MMCM must be in the same CMT column, and they are adjacent to
# each other (vertically), if the CLOCK_DEDICATED_ROUTE=BACKBONE constraint is NOT set

#<<<<<< Clock Rule: rule_multi_slr_bufg >>>>
# Rule Description: For a multi-SLR device, a maximum of one BUFG at same relative position in different
# SLRs can be used, that is two BUFG sites whose Y-index differs by a multiple of 32 cannot be used
# at the same time.

# <<<<< Clock Rule: rule_cascaded_bufg >>>>
# Rule Description: Cascaded bufg (bufg->bufg) must be adjacent and cyclic

 

 

And lastly you can overide some of these rules using TCL; e.g:

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets -of [get_pins -of [get_cells REFCLK_ALT_IBUFDS] -filter {DIRECTION == OUT}]]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_pins -of [get_cells REFCLK_ALT_IBUFDS] -filter {DIRECTION == OUT}]]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk200]

 

Digital Design Golden Rule: If its not tested - its broken.
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Visitor
Visitor
15,338 Views
Registered: ‎01-09-2013

Thanks for your answer.

 

It is very helpful for me. :)

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