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cassandra
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Adventurer
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Registered: ‎05-11-2018

Placement Error IBUFDS to BUFG

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Hello,

I have encountered the following errors during the placement root step:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tb_dco3] >

	IBUFDS_DCO_3 (IBUFDS.O) is locked to IOB_X0Y334
	 and tb_dco3_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tb_dco4] >

	IBUFDS_DCO_4 (IBUFDS.O) is locked to IOB_X1Y56
	 and tb_dco4_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

tb_dco3 and tb_dco4 are the outputs of IBUFS buffers and are used to as a clock to sample data.

I don't understand why i have these errors on tb_dco3 and tb_dco4 and not on the signals tb_dco1 and tb_dco2 who are absolutely symmetric to tb_dco3 and tb_dco4

Has anyone seen this kind of error?

(I know that it is better to use BUFR for data sampling my an external source clock for timing performance, but i thought that it was possible to use a BUFG after the output of a BUFDS to sample data? Am i wrong?)

Here is the schematic of my design below :

 

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827 Views
Registered: ‎01-22-2015

@cassandra

Sometimes these warnings indicate that you are bringing a clock into the FPGA via FPGA pins that are NOT clock-capable.  Are the pins, dco_p and dco_n, a clock-capable pin-pair?

Of course, we should always try to use clock-capable pins for bringing clocks into the FPGA.  -because there are dedicated routing paths from these pins to the FPGA clocking resources  -and it keeps clock jitter low and allows the MMCM (if you were using one) to do the delay compensation described <here>.

However, if you are stuck with using non-clock-capable pins then it is not a disaster. The warnings you received simply indicate that your clock will not be optimal. The warnings also ask you to give Vivado permission to go ahead with routing by placing the following constraints in your project’s XDC file.

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tb_dco3]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tb_dco4]

Mark

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1 Reply
828 Views
Registered: ‎01-22-2015

@cassandra

Sometimes these warnings indicate that you are bringing a clock into the FPGA via FPGA pins that are NOT clock-capable.  Are the pins, dco_p and dco_n, a clock-capable pin-pair?

Of course, we should always try to use clock-capable pins for bringing clocks into the FPGA.  -because there are dedicated routing paths from these pins to the FPGA clocking resources  -and it keeps clock jitter low and allows the MMCM (if you were using one) to do the delay compensation described <here>.

However, if you are stuck with using non-clock-capable pins then it is not a disaster. The warnings you received simply indicate that your clock will not be optimal. The warnings also ask you to give Vivado permission to go ahead with routing by placing the following constraints in your project’s XDC file.

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tb_dco3]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tb_dco4]

Mark

View solution in original post