Poor Placement between an IO and BUFG

[sathyajit92@gmail.com]

Hi,

I'm using the Aritx 7 FPGA for a simple counter test:

RTL:

module scope_testing(clock,a);

input clock;
output a;

/// BUFFER CLOCK Connection from IO PIN
wire ref_clk_buf;

BUFG REF_BUFG(.O(ref_clk_buf),.I(clock));

reg [5:0]divide=0;
reg a=0;

always@(posedge ref_clk_buf)
begin
divide<=divide+1;
if(divide==10)
begin
a<=~a;
divide<=0;
end
end
endmodule

XDC:

create_clock -period 10.000 -name clock -waveform {0.000 5.000} [get_ports clock];

set_property PACKAGE_PIN P16 [get_ports clock];
set_property PACKAGE_PIN P26 [get_ports a];
set_property IOSTANDARD LVCMOS33 [get_ports clock];
set_property IOSTANDARD LVCMOS33 [get_ports a];

PLCK-12#1 Error
Clock Placer Checks
Poor placement for routing between an IO pin and BUFG.
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clock_IBUF] >

clock_IBUF_inst (IBUF.O) is locked to P16
REF_CLK_BUF (BUFG.I) cannot be placed

[arpansur]

Hi sathyajit92@gmail.com,

What is the device package you are using?

[sathyajit92@gmail.com]

I'm using the AC 701 Eval Board with the package xc7a200tfbg676-2. I'm not sure why the error:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clock_IBUF] >

clock_IBUF_inst (IBUF.O) is locked to IOB_X0Y143
and REF_BUFG (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y7

Please help, thanks!

[arpansur]

HI sathyajit92@gmail.com,

You are getting this error because P16 is not a clock pin. It's N pin of differential pair.

You can find package pin descriptions in http://www.xilinx.com/support/packagefiles/a7packages/xc7a200tfbg676pkg.txt

Please go through page-85 of below link for master xdc of AC701
http://www.xilinx.com/support/documentation/boards_and_kits/ac701/ug952-ac701-a7-eval-bd.pdf

Try with sysclk->ibufds->bufg

[arpansur · Accepted solution]

Hi sathyajit92@gmail.com,

Below is a modified code and XDC constraints

module scope_testing(clock_p,clock_n,a);
input clock_p;
input clock_n;
output a;
/// BUFFER CLOCK Connection from IO PIN
wire temp;
wire ref_clk_buf;
IBUFDS #(
.DIFF_TERM("FALSE"), // Differential Termination
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
) IBUFDS_inst (
.O(temp), // Buffer output
.I(clock_p), // Diff_p buffer input (connect directly to top-level port)
.IB(clock_n) // Diff_n buffer input (connect directly to top-level port)
);
BUFG REF_BUFG(.O(ref_clk_buf),.I(temp));

reg [5:0]divide=0;
reg a=0;
always@(posedge ref_clk_buf)
begin
divide<=divide+1;
if(divide==10)
begin
a<=~a;
divide<=0;
end
end
endmodule

set_property PACKAGE_PIN R3 [get_ports clock_p]
set_property IOSTANDARD LVDS_25 [get_ports clock_p]
set_property PACKAGE_PIN P3 [get_ports clock_n]
set_property IOSTANDARD LVDS_25 [get_ports clock_n]
set_property PACKAGE_PIN M26 [get_ports a]
set_property IOSTANDARD LVCMOS33 [get_ports a]

[sathyajit92@gmail.com]

 Thank you Arpan. I have two quick clarifications:

a. How to add the create clock constraint for the LVDS pair? Should I be adding only for the P side pin i.e. R3 pin?

b. Why is my original design not correct? P16 is reported to be a single ended clock in the user guide as follows:

P16 FPGA_EMCCLK LVCMOS33 U40 3 SiT8103 3.3V Single-Ended LVCMOS 90 MHz Fixed Frequency Oscillator (SiTime)

Thank you once again,
Sathyajit

[arpansur]

Hi sathyajit92@gmail.com,

Constrain only P-side http://www.xilinx.com/support/answers/57109.html