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Visitor davewen
Registered: ‎05-19-2016

Populate all inferred block ram with random data

Hi all,


I have a design that relies heavily on block ram which I need to populate with random data. I understand that block ram can have power-on initial values and know the VHDL syntax to specify this default. What, then, do I need to do to populate each instance of inferred block ram with different random data?


Also, what happens if I read block ram before writing anything to it --- am I guaranteed to see 000.., fff... or random bits?



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1 Reply
Registered: ‎01-08-2012

Re: Populate all inferred block ram with random data

The block ram is always initialised from the bitstream when you configure the FPGA.  I'm fairly sure you don't have a choice about that (unless you are using PR, which you probably aren't).


If you don't tell Vivado (etc) what this initial value should be, it will choose all zeros for you.  It will never be "random".



I'm not quite sure what system-level problem you're actually trying to solve here.


I suspect you are using "random" as an adjective to mean "not all zero" because actual generation of true randomness is not something that you can program into the bitstream, short of editing the bitstream (with some data from an entropy source) prior to loading it into the FPGA.


OTOH, if you actually do need true randomness, e.g. for a cryptographic key, then you will need an entropy generator inside the FPGA design; relying on RAM initial values is not the way to do that.

BTW, almost all of the FPGA entropy generator designs that you can find for free are crap, including the ones published by Xilinx and described as "excellent" on these very forums.  (Hint: ask for their NIST or BSI certification - they won't have it.)


If you're merely after a way of determining whether a RAM location has been written since the FPGA bitstream was loaded, I suggest making the RAM one bit wider.  This extra bit serves as a flag.  It will start at zero.  Every write will set it to '1'.  If you ever read it as '0', you know that RAM location hasn't been written since the FPGA was loaded.

(You can also do something similar by treating the flag bit as a parity bit.  Choose your parity function so that the initial all zeros value will be seen as an error, etc.)