cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
360 Views
Registered: ‎09-16-2019

Possible failed pin causing issues in circuit

Jump to solution

Hello, 

I have a system with a 7 series FPGA. In the system there are various regulators with "power good" outputs that are connected to the enable pins of downstream regulators for the purpose of sequencing the supplies. One of the regulators in the sequencing chain is not generating a proper "power good" signal voltage even though it is receiving the correct input voltage and has also be replaced. This node with the "power good" signal is also connected to an input to the FPGA for monitoring purposes. An engineer I am working with speculates that the FPGA is somehow affecting this node. If this FPGA pin were to be damaged, would it be possible that this is causing the issue we are seeing? Note that the system was working before this issue occurred.   

Thank you, 

David 

0 Kudos
1 Solution

Accepted Solutions
drjohnsmith
Teacher
Teacher
332 Views
Registered: ‎07-09-2009

quiet probably

read the data sheet 

unpowered FPGAs any voltage is above the limit.

    Your then into current limiting the possible current into the FPGA to stop damage to the input pin,

Also remember, till the the FPGA is configured, then any pin is undefined. 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

4 Replies
drjohnsmith
Teacher
Teacher
351 Views
Registered: ‎07-09-2009

When damaged, 

   anything is possible.

the question is , what caused the damage.

    I'd say its as near impossible that it was the FPGA that caused the problem,

Can I clarify,

    there is a spec on the voltage allowed into any IO pin of the FPGA,

This is referenced to the various FPGA power supplies, 

   Its unclear as to if you are applying this power good signal to the F{GA as a voltage that is there before the FPGA is powered ?

      If so m you are not as per data sheet.

Its easily done, 

Suggest lift the pin on the PSU, see if the power good works without the FPGA connected.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
349 Views
Registered: ‎09-16-2019

Yes, that input pin is being powered before the bank is powered. You believe this will cause damage? 

0 Kudos
drjohnsmith
Teacher
Teacher
333 Views
Registered: ‎07-09-2009

quiet probably

read the data sheet 

unpowered FPGAs any voltage is above the limit.

    Your then into current limiting the possible current into the FPGA to stop damage to the input pin,

Also remember, till the the FPGA is configured, then any pin is undefined. 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

324 Views
Registered: ‎09-16-2019

Thank you for your information. 

0 Kudos