cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Newbie
Newbie
721 Views
Registered: ‎09-25-2018

Power Down Sequence for the Ultrascale XCKU060

Hi,

 

1) Is there any power down sequencing concerns with the Ultrascale XCKU060 FPGA?

2) Is there any backwards biasing concerns that might damage the part?

 

Thanks,

Mike

0 Kudos
2 Replies
Highlighted
Teacher
Teacher
695 Views
Registered: ‎07-09-2009

1)  power down sequence,  just turn off . e.g. if the mains disappeared, the chips have to survive.

       

2) chips are not designed to be back powered, it heats up the IOB's, to much heat kills or at best shortens the life of the chip.

      data sheets have references on limits 

 

 The bottom line is about heat.

   power up / down, what the designers dont want is some supplies on, other off for long periods. 

     

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
685 Views
Registered: ‎06-30-2010

the recommend power on and off sequence is given in the data sheet. If that is NOT followed there is no potential for damage to the device but you could see more power on current of have a glitch on the IOs during the power on or off sequence.

However as @drjohnsmith mentions you should do the sequence within the allotted time there should not be one supply on for long periods

For 7-series we have the Tvcco2vccaux spec that could lead to IO damage if exceed but that has being removed in US / US+.
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos