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Observer jdabbs003
Observer
735 Views
Registered: ‎10-05-2016

Power Sequencing

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In the Artix-7, is it be ok to tie VCCINT, VCCBRAM, and MGTAVCC together to the same 1.0V power supply, as long as the power supply can handle the load?  Or do they need to be separate?

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Moderator
Moderator
630 Views
Registered: ‎09-18-2014

Re: Power Sequencing

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Jdabbs003,

 

I am assuming you are using the GTs here. If not the answer is you can tie the three rails. If using the GTs, you can* do that as long as you can guarantee your design can maintain the rail specifications especially MGT rails in your application application environment. However the reality of the situation in most cases is that in particular for transceivers are much more sensitive to noise as you are working literally with a hundred picoseconds of margin. To maintain the 10mVpk-pk noise requirement as well as the 3% supply requirement it is much easier done with a dedicated supply. Not only that VCCINT is usually a fairly noisy rail as it supplies a majority of the FPGA resources. Noise coupling between the rails if not filtered properly will make it difficult to implement cleanly. Now if you can meet those requirements with your power distribution set up great, but that is difficult to do in most cases and having separate rails makes it that much easier to meet the specifications. 

 

Regards,

T

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6 Replies
Voyager
Voyager
684 Views
Registered: ‎02-01-2013

Re: Power Sequencing

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It is permissible to tie all of those rails together.  Ordinarily, however, the V-MGTVCC is generated from a quieter source--like an LDO--instead of a standard switching supply that one uses to power digital rails. 

Note that V-MGTVCC requires a tighter voltage regulation (+/-3%) than do the other rails (+/-5%), so they'd all have to come from a unified +/-3% source if they were combined.

-Joe G.

 

Moderator
Moderator
631 Views
Registered: ‎09-18-2014

Re: Power Sequencing

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Jdabbs003,

 

I am assuming you are using the GTs here. If not the answer is you can tie the three rails. If using the GTs, you can* do that as long as you can guarantee your design can maintain the rail specifications especially MGT rails in your application application environment. However the reality of the situation in most cases is that in particular for transceivers are much more sensitive to noise as you are working literally with a hundred picoseconds of margin. To maintain the 10mVpk-pk noise requirement as well as the 3% supply requirement it is much easier done with a dedicated supply. Not only that VCCINT is usually a fairly noisy rail as it supplies a majority of the FPGA resources. Noise coupling between the rails if not filtered properly will make it difficult to implement cleanly. Now if you can meet those requirements with your power distribution set up great, but that is difficult to do in most cases and having separate rails makes it that much easier to meet the specifications. 

 

Regards,

T

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Observer jdabbs003
Observer
623 Views
Registered: ‎10-05-2016

Re: Power Sequencing

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In this case, the GT's are being used as a 1x PCIe transceiver.  We were hoping that tying VCCINT to MGTVCC through an LC filter would work, but maybe a separate LDO would work better.

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Registered: ‎01-08-2012

Re: Power Sequencing

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One of my Zynq 7 designs ties all three rails together.  As has already been pointed out, this did require extra attention in the design to meet the regulation requirements of MGTAVCC.  There were costs associated with that.

For me, the deciding factor to go this way was the design of the power planes under the FPGA.  A common rail meant an unbroken plane.  I didn't have any spare Cu on a layer that was convenient for bringing in yet another rail under the FPGA, and it was starting to look like I would need to add an extra pair of layers to the PCB.  Adding layers adds a lot of cost, so I decided not to do that.

Observer jdabbs003
Observer
591 Views
Registered: ‎10-05-2016

Re: Power Sequencing

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Thanks for the insight.  If I may ask, in this design, what were you using the MGT's for?

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571 Views
Registered: ‎01-08-2012

Re: Power Sequencing

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PCIe root complex.  I used 4 lanes.  It might have only been Gen 1 though (2.5GT/s).