02-15-2019 04:25 AM - edited 02-15-2019 04:48 AM
I am using Vivado 2018.1 for analyzing the power of my design. Although it contains a number of designs, power report gives me awkward results. For making a proper power analysis I followed ug997-vivado power analysis optimization tutorial , I implemented the design, gave the constraints for clock and all inputs properly, made a post-implementation functional simulation to create saif file and reported the power with saif but the result was almost the same. Struggling point is that it gives very small dynamic power (in typical process and commercial grade; with saif 0.015 W, without saif 0.003 W) which makes me unsure about its correctness although its confidence level is high. Another point is, when I implement a subblock of my design (memory of the design), interestingly it gives more dynamic power (without saif 0.025) than the whole design! How is it possible, actually I did not understand. I also tried the same analysis in Vivado 2017.1 , too, but the result is the same. I used Zedboard as FPGA, switched the board type as well ( used KC705 , too), however, the result did not change again. Are these power analysis really true? I attached snapshots of the power report for both whole design and subblock, any idea and comment about this issue and power analysis in general would be helpful for me.
Thank in advance.
02-15-2019 08:58 AM - edited 02-15-2019 08:59 AM
As you mentioned you have also tried power estimation with SAIF but it reported results same.
Please check for https://www.xilinx.com/video/hardware/power-estimation-analysis-using-vivado.html , https://www.xilinx.com/video/hardware/power-optimization-using-vivado.html and https://www.xilinx.com/support/answers/63015.html for getting accurate power estimation results.
02-19-2019 01:27 AM
My problem is still not solved, unfortunately.
log_saif [ get_objects -r * ]
02-20-2019 12:28 AM
You can click BRAM and get more detail from the utilization details why there is a difference there. Or you can export xpe from Vivado and import xpe to XPE spreadsheet, An example:
report_power -file routed.pwr -xpe design_top.xpe
Without SAIF file, the more accurate the dynamic power is if the more switching is input on switching page. If confidence is low, how accurate the switching activity is for control signal by selecting Tools > Power Constraints Advisor.
With SAIF file, ensure test vectors and inputs to the simulation represent the expected behavior, otherwise this will lead to a different switching and static activity.