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Registered: ‎06-07-2018

Power analysis

Hi everyone,

I am using Vivado 2018.1 for analyzing the power of my design. Although it contains a number of designs, power report gives me awkward results. For making a proper power analysis I followed ug997-vivado power analysis optimization tutorial , I implemented the design, gave the constraints for clock and all inputs properly, made a post-implementation functional simulation to create saif file and reported the power with saif but the result was almost the same. Struggling point is that it gives very small dynamic power (in typical process and commercial grade; with saif 0.015 W, without saif 0.003 W) which makes me unsure about its correctness although its confidence level is high. Another point is, when I implement a subblock of my design (memory of the design), interestingly it gives more dynamic power (without saif 0.025) than the whole design! How is it possible, actually I did not understand. I also tried the same analysis in Vivado 2017.1 , too, but the result is the same. I used Zedboard as FPGA, switched the board type as well ( used  KC705 , too), however, the result did not change again. Are these power analysis really true? I attached snapshots of the power report for both whole design and subblock, any idea and comment about this issue and power analysis in general would be helpful for me.

Thank in advance.




whole design_power.PNG
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3 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎03-07-2018

Re: Power analysis

Hello @ibrahim_tastan

As you mentioned you have also tried power estimation with SAIF but it reported results same.

  • Kindly generate SAIF file as mentioned in AR# 52632 and UG900 (v2018.2) June 6, 2018 (Page116~117)
  • Kindly check AR# 55595 how different type of simulation affects accuracy of power analysis.
  • If your design includes any encrypted IP/Blocks then simulator will not dump the SAIF information for those IP/Blocks and for any internal blocks within the encrypted hierarchy. This incomplete SAIF information might affect the power estimation accuracy.
  • Kindly provide SAIF annotation summary which show the number of design nets matched. TCL command read_saif provides this information. Check UG907 (v2018.2) June 6, 2018 (Page 69)
  • Check for static or user entered values as they have more priority in Vivado analysis tool.


Please check for https://www.xilinx.com/video/hardware/power-estimation-analysis-using-vivado.html , https://www.xilinx.com/video/hardware/power-optimization-using-vivado.html and https://www.xilinx.com/support/answers/63015.html for getting accurate power estimation results. 



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Registered: ‎06-07-2018

Re: Power analysis

Hello @bpatil,

My problem is still not solved, unfortunately.

  • I generated SAIF file in post-implementation functional simulation (as explained in AR# 52632 ) with the comments below . 

open_saif  my_design.saif

log_saif  [ get_objects -r  * ]

source my_tcl.tcl


  • I added saif annotation summary below. As seen all nets are matched.
  • My design does not contain any encrypted IP/Blocks 
  • My constraint file only includes create_clock command; input, output ports definitions and iobank definitions for these ports.



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Xilinx Employee
Xilinx Employee
Registered: ‎08-25-2010

回复: Power analysis

Hi @ibrahim_tastan,

You can click BRAM and get more detail from the utilization details why there is a difference there. Or you can export xpe from Vivado and import xpe to XPE spreadsheet, An example:

report_power -file routed.pwr -xpe design_top.xpe

Without SAIF file, the more accurate the dynamic power is if the more switching is input on switching page. If confidence is low, how accurate the switching activity is for control signal by selecting Tools > Power Constraints Advisor.

With SAIF file, ensure test vectors and inputs to the simulation represent the expected behavior, otherwise this will lead to a different switching and static activity.

Don't forget to reply, kudo, and accept as solution.
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