Power reference design

[syssurge]

I´m designing my own input voltage regulator and I´m looking for a simple power reference schematic to help me along, preferably with example part numbers, to power all VCCINT on a XC7K420T-2FFG901I. I´ve designed a input voltage generator using a Schottky diode, 1500 mA fuse, a 1.0V voltage regulator, and two 10u capacitors, but I´m worried it´s too simple a design for a FPGA like this. All help appreciated. Thank you.

[drjohnsmith]

Have you checked out what power you are expecting to use
https://www.xilinx.com/products/technology/power/xpe.html

if in doubt, check out the many schematics of boards out there,

This has guide lines on de coupling.

https://www.xilinx.com/support/documentation/user_guides/ug483_7Series_PCB.pdf

https://www.xilinx.com/support/documentation/application_notes/xapp158.pdf

[barriet]

Good advice above.

You can also find a variety of power example designs by FPGA family here: https://www.xilinx.com/products/technology/power.html#partners

Cheers,

bt

[syssurge]

Xilinx Power Estimator (XPE) download link for the 7-series is dead, once you agree to the license agreement it says "file not found".

Closest reference design in your links is the Artix-7, but I requested a Kintex 7 reference design - not sure if this was helpful.

Thanks anyways.

[barriet · Accepted solution]

I just checked the 7 series XPE link listed (https://www.xilinx.com/member/forms/download/power-estimator-license.html?cid=b19eb944-1f6b-4183-a2aa-d017fe02e766&filename=7_Series_XPE_2019_1_2.zip) and it worked for me - 7_Series_XPE_2019_1_2.zip

The 7 series FPGA are a unified architecture - the Kintex-7 (K7) should be a good close fit for Artix-7 (A7)... The differences here between families are going to be transceivers (GTX, GTH, GTZ, none), device size (and corresponding power), package (and thermal performance) and fabric performance (K7/V7 are faster/more power than the slower tuned A7/S7) - the usual voltage rails Vccint/Vccaux/Vccauxio/Vcco should be the same - though the latter Vcco depend on the design/bank IO standard.

Check the data sheet because the -3E and -1LI/-2LI may have slightly different voltages than the usual -1I/-1C/-2I/-2C. The voltage scaled parts (-L) can run at a lower voltage for dynamic power savings and have a different corresponding max static power (based on Tj) based on screening.

Cheers,

bt

== minor clarification

[barriet]

It is also worth noting from a development board perspective that many of our boards are developed before silicon comes back in house and final characterization is done - so they may not agree with our later public documentation on decoupling requirements, etc. And there's a lot of 3rd party development boards that we likely did not have a hand in developing or even reviewing.