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binayak_shrestha
Adventurer
Adventurer
1,013 Views
Registered: ‎10-05-2015

Powering up Zynq 7000 SoC

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Hi,

When powering Zynq 7000 SoC (Z-7045), if the the power on/off sequencing of PS and PL sections are being followed as given in DS191, can we begin the powering on the rails of PL and PS section at the same time? Or, is there any need to power up one section (PL or PS) completely before powering up the other one?

Same doubt while powering down.

Thanks,

Binayak

 

 

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bpatil
Xilinx Employee
Xilinx Employee
516 Views
Registered: ‎03-07-2018

Hi @binayak_shrestha 

Please check  https://www.xilinx.com/support/answers/57819.html 

It is fine to combine PS and PL power rails, if combined voltage rails meets the data sheet requirements for voltage and tolerance all the time.  

Regards,
Bhushan

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9 Replies
allanherriman
Mentor
Mentor
994 Views
Registered: ‎01-08-2012

Yes, it's quite ok to power them at the same time.  My designs share rails between the PS and PL where possible.

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binayak_shrestha
Adventurer
Adventurer
988 Views
Registered: ‎10-05-2015

Hi Allan,

Thanks for the reply. Sharing of power rails was one of the reasons I had in mind. The other reason was to accomodate PMIC supplies. However, the EVM (ZC-706) separates the PL and PS power supplies. 

Thanks,

Binayak

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binayak_shrestha
Adventurer
Adventurer
964 Views
Registered: ‎10-05-2015

Hi,

Can any Xilinx employee verify this:

- a PL voltage rail and a PS voltage rail can be fed through a same power-ground power bus?

 

Thanks,

Binayak

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joe306
Scholar
Scholar
691 Views
Registered: ‎12-07-2018
Hello, I will be doing a Zynq-7000 design soon and I am researching the power up sequence. Did you use a microcontroller for the sequencing?
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allanherriman
Mentor
Mentor
672 Views
Registered: ‎01-08-2012

I usually do this the simple way: I just cascade the PGOOD output from one rail's DC/DC converter into the ENABLE input of the next one.

It works.  It doesn't require any special manufacturing steps.

joe306
Scholar
Scholar
662 Views
Registered: ‎12-07-2018
Sounds reasonable?
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allanherriman
Mentor
Mentor
646 Views
Registered: ‎01-08-2012

It works for me.  On the other hand, if you already have an "always-on" microcontroller on your board for some other purpose (e.g. battery management) you might as well use that.

The Zynqs don't need complicated sequencing though.  I stagger the power on times of my various rails to reduce the peak inrush current, rather than for any FPGA-related reason.

joe306
Scholar
Scholar
625 Views
Registered: ‎12-07-2018
Thank you very much.
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bpatil
Xilinx Employee
Xilinx Employee
517 Views
Registered: ‎03-07-2018

Hi @binayak_shrestha 

Please check  https://www.xilinx.com/support/answers/57819.html 

It is fine to combine PS and PL power rails, if combined voltage rails meets the data sheet requirements for voltage and tolerance all the time.  

Regards,
Bhushan

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