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Registered: ‎07-12-2019

Probelm in interfacing the ADC with FPGA

Hello everyone,,

Dear Sir/Madam,


I am interfacing ADC board with zynq FPGA board.

The design has IDELAYCTRL and IDELAY2 with fixed delay format, design is working but for sometimes ADC data is coming wrong (glitches or constant data), for the same delay if i do rebuild behaviour is changing.


I think configuration of DELYAS are not doing properly, can anyone support to stabilize my design....

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Registered: ‎06-21-2017

Re: Probelm in interfacing the ADC with FPGA

You need to supply more information for anyone to help.  What FPGA and which ADC?  What timing constraints do you have?   What is your design for the input from the ADC, either code or the synthesized schematic, or both.

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