03-03-2020 03:17 AM
I would like to generate variable frequency using Artix-7 from 1.6 MHz to 2.3 MHz with a resolution of 0.001 MHz. My clock frequency is 100 MHz. I am able to generate fix frequency in this range using reference design of MMCM-DRP access. But I am unable to vary CLKFBOUT_MULT_F, DIVCLK_DIVIDE, CLKOUT0_DIVIDE_F using program. These parameter accept only constant value. Perhaps, I am unable to change verilog code.
Please suggest better way to generate the variable frequency from 1.6 MHz to 2.3 MHz with a resolution of 0.001 MHz.
03-04-2020 12:13 AM
What do you want to use the frequency for? You might want to look into different DDS-Style algorithms to generate either the clock (if you want to output the waveform to another IC) or a clock enable (if you want to use it as an internal clock).
Beware that this basically distributes the frequency error around at a granularity of 1 clock cycle of your reference clock, so in your case, you will see jitter in increments of 10 ns.
03-04-2020 04:23 AM
If you have an Ultrascale device, you could probably multiply your 100MHz clock up to 400MHz and use @klasha's DDS idea. This would reduce the deterministic jitter to 2.5nS. What jitter is acceptable? Just an observation, you are looking at producing clocks with a period difference of 2.5x10e-16 seconds. I don't think that you could run a PLL in an FPGA fast enough to give you the resolution you want.
03-04-2020 05:17 AM