cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
289 Views
Registered: ‎09-02-2019

Problem while generating frequency generation

I would like to generate variable  frequency using  Artix-7 from 1.6 MHz to 2.3 MHz with a resolution of 0.001 MHz. My clock frequency is 100 MHz. I am able to generate fix frequency in this range using reference design of MMCM-DRP access. But I am unable to vary CLKFBOUT_MULT_F, DIVCLK_DIVIDE, CLKOUT0_DIVIDE_F using program. These parameter accept only constant value. Perhaps, I am unable to change verilog code. 

Please suggest better way to generate the variable frequency from 1.6 MHz to 2.3 MHz with a resolution of 0.001 MHz.

0 Kudos
4 Replies
Highlighted
Adventurer
Adventurer
208 Views
Registered: ‎05-23-2018

Re: Problem while generating frequency generation

What do you want to use the frequency for? You might want to look into different DDS-Style algorithms to generate either the clock (if you want to output the waveform to another IC) or a clock enable (if you want to use it as an internal clock).

Beware that this basically distributes the frequency error around at a granularity of 1 clock cycle of your reference clock, so in your case, you will see jitter in increments of 10 ns.

Highlighted
192 Views
Registered: ‎09-02-2019

Re: Problem while generating frequency generation

10 ns jitter is not acceptable 

0 Kudos
Highlighted
165 Views
Registered: ‎06-21-2017

Re: Problem while generating frequency generation

If you have an Ultrascale device, you could probably multiply your 100MHz clock up to 400MHz and use @klasha's DDS idea.  This would reduce the deterministic jitter to 2.5nS.  What jitter is acceptable?  Just an observation, you are looking at producing clocks with a period difference of 2.5x10e-16 seconds.  I don't think that you could run a PLL in an FPGA fast enough to give you the resolution you want. 

0 Kudos
Highlighted
Teacher
Teacher
153 Views
Registered: ‎07-09-2009

Re: Problem while generating frequency generation

At first glance what I want to achieve looks impossible in a fpga.
But
There are some very clever people on here.
Give them some idea as to your total system design , and they might be able to stear you .
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos